blob: 19bd182fa927358b8f20f1ad2c0318bda17fee7a [file] [log] [blame]
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8/* Marvell CP110 SoC COMPHY unit driver */
9
10#include <debug.h>
11#include <delay_timer.h>
12#include <errno.h>
13#include <mmio.h>
14#include <mvebu_def.h>
15#include <spinlock.h>
16#include "mvebu.h"
17#include "comphy-cp110.h"
18
19/* #define DEBUG_COMPHY */
20#ifdef DEBUG_COMPHY
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010021#define debug(format...) printf(format)
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +030022#else
23#define debug(format, arg...)
24#endif
25
26/* A lane is described by 4 fields:
27 * - bit 1~0 represent comphy polarity invert
28 * - bit 7~2 represent comphy speed
29 * - bit 11~8 represent unit index
30 * - bit 16~12 represent mode
31 * - bit 17 represent comphy indication of clock source
32 * - bit 19-18 represents pcie width (in case of pcie comphy config.)
33 * - bit 31~20 reserved
34 */
35
36#define COMPHY_INVERT_OFFSET 0
37#define COMPHY_INVERT_LEN 2
38#define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, \
39 COMPHY_INVERT_LEN)
40#define COMPHY_SPEED_OFFSET (COMPHY_INVERT_OFFSET + COMPHY_INVERT_LEN)
41#define COMPHY_SPEED_LEN 6
42#define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, \
43 COMPHY_SPEED_LEN)
44#define COMPHY_UNIT_ID_OFFSET (COMPHY_SPEED_OFFSET + COMPHY_SPEED_LEN)
45#define COMPHY_UNIT_ID_LEN 4
46#define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, \
47 COMPHY_UNIT_ID_LEN)
48#define COMPHY_MODE_OFFSET (COMPHY_UNIT_ID_OFFSET + COMPHY_UNIT_ID_LEN)
49#define COMPHY_MODE_LEN 5
50#define COMPHY_MODE_MASK COMPHY_MASK(COMPHY_MODE_OFFSET, COMPHY_MODE_LEN)
51#define COMPHY_CLK_SRC_OFFSET (COMPHY_MODE_OFFSET + COMPHY_MODE_LEN)
52#define COMPHY_CLK_SRC_LEN 1
53#define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, \
54 COMPHY_CLK_SRC_LEN)
55#define COMPHY_PCI_WIDTH_OFFSET (COMPHY_CLK_SRC_OFFSET + COMPHY_CLK_SRC_LEN)
56#define COMPHY_PCI_WIDTH_LEN 3
57#define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, \
58 COMPHY_PCI_WIDTH_LEN)
59
60#define COMPHY_MASK(offset, len) (((1 << (len)) - 1) << (offset))
61
62/* Macro which extracts mode from lane description */
63#define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> \
64 COMPHY_MODE_OFFSET)
65/* Macro which extracts unit index from lane description */
66#define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> \
67 COMPHY_UNIT_ID_OFFSET)
68/* Macro which extracts speed from lane description */
69#define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> \
70 COMPHY_SPEED_OFFSET)
71/* Macro which extracts clock source indication from lane description */
72#define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> \
73 COMPHY_CLK_SRC_OFFSET)
74/* Macro which extracts pcie width indication from lane description */
75#define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> \
76 COMPHY_PCI_WIDTH_OFFSET)
77
78#define COMPHY_SATA_MODE 0x1
79#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
80#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
81#define COMPHY_USB3H_MODE 0x4
82#define COMPHY_USB3D_MODE 0x5
83#define COMPHY_PCIE_MODE 0x6
84#define COMPHY_RXAUI_MODE 0x7
85#define COMPHY_XFI_MODE 0x8
86#define COMPHY_SFI_MODE 0x9
87#define COMPHY_USB3_MODE 0xa
88#define COMPHY_AP_MODE 0xb
89
90/* COMPHY speed macro */
91#define COMPHY_SPEED_1_25G 0 /* SGMII 1G */
92#define COMPHY_SPEED_2_5G 1
93#define COMPHY_SPEED_3_125G 2 /* SGMII 2.5G */
94#define COMPHY_SPEED_5G 3
95#define COMPHY_SPEED_5_15625G 4 /* XFI 5G */
96#define COMPHY_SPEED_6G 5
97#define COMPHY_SPEED_10_3125G 6 /* XFI 10G */
98#define COMPHY_SPEED_MAX 0x3F
99/* The default speed for IO with fixed known speed */
100#define COMPHY_SPEED_DEFAULT COMPHY_SPEED_MAX
101
102/* Commands for comphy driver */
103#define COMPHY_COMMAND_DIGITAL_PWR_OFF 0x00000001
104#define COMPHY_COMMAND_DIGITAL_PWR_ON 0x00000002
105
106#define COMPHY_PIPE_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + 0x120000)
107
108/* System controller registers */
109#define PCIE_MAC_RESET_MASK_PORT0 BIT(13)
110#define PCIE_MAC_RESET_MASK_PORT1 BIT(11)
111#define PCIE_MAC_RESET_MASK_PORT2 BIT(12)
112#define SYS_CTRL_UINIT_SOFT_RESET_REG 0x268
113#define SYS_CTRL_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + 0x440000)
114
115/* DFX register spaces */
116#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET (0)
117#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK (0x1 << \
118 SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET)
119#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET (1)
120#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK (0x1 << \
121 SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET)
122#define SAR_STATUS_0_REG 200
123#define DFX_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + DFX_BASE)
124
125/* The same Units Soft Reset Config register are accessed in all PCIe ports
126 * initialization, so a spin lock is defined in case when more than 1 CPUs
127 * resets PCIe MAC and need to access the register in the same time. The spin
128 * lock is shared by all CP110 units.
129 */
130spinlock_t cp110_mac_reset_lock;
131
132enum reg_width_type {
133 REG_16BIT = 0,
134 REG_32BIT,
135};
136
137enum {
138 COMPHY_LANE0 = 0,
139 COMPHY_LANE1,
140 COMPHY_LANE2,
141 COMPHY_LANE3,
142 COMPHY_LANE4,
143 COMPHY_LANE5,
144 COMPHY_LANE_MAX,
145};
146
147/* These values come from the PCI Express Spec */
148enum pcie_link_width {
149 PCIE_LNK_WIDTH_RESRV = 0x00,
150 PCIE_LNK_X1 = 0x01,
151 PCIE_LNK_X2 = 0x02,
152 PCIE_LNK_X4 = 0x04,
153 PCIE_LNK_X8 = 0x08,
154 PCIE_LNK_X12 = 0x0C,
155 PCIE_LNK_X16 = 0x10,
156 PCIE_LNK_X32 = 0x20,
157 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
158};
159
160static inline uint32_t polling_with_timeout(uintptr_t addr,
161 uint32_t val,
162 uint32_t mask,
163 uint32_t usec_timeout,
164 enum reg_width_type type)
165{
166 uint32_t data;
167
168 do {
169 udelay(1);
170 if (type == REG_16BIT)
171 data = mmio_read_16(addr) & mask;
172 else
173 data = mmio_read_32(addr) & mask;
174 } while (data != val && --usec_timeout > 0);
175
176 if (usec_timeout == 0)
177 return data;
178
179 return 0;
180}
181
182static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask)
183{
184 debug("<atf>: WR to addr = %#010lx, data = %#010x (mask = %#010x) - ",
185 addr, data, mask);
186 debug("old value = %#010x ==> ", mmio_read_32(addr));
187 mmio_clrsetbits_32(addr, mask, data);
188
189 debug("new val %#010x\n", mmio_read_32(addr));
190}
191
192/* Clear PIPE selector - avoid collision with previous configuration */
193static void mvebu_cp110_comphy_clr_pipe_selector(uint64_t comphy_base,
194 uint8_t comphy_index)
195{
196 uint32_t reg, mask, field;
197 uint32_t comphy_offset =
198 COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index;
199
200 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset;
201 reg = mmio_read_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET);
202 field = reg & mask;
203
204 if (field) {
205 reg &= ~mask;
206 mmio_write_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET,
207 reg);
208 }
209}
210
211/* Clear PHY selector - avoid collision with previous configuration */
212static void mvebu_cp110_comphy_clr_phy_selector(uint64_t comphy_base,
213 uint8_t comphy_index)
214{
215 uint32_t reg, mask, field;
216 uint32_t comphy_offset =
217 COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index;
218
219 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset;
220 reg = mmio_read_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET);
221 field = reg & mask;
222
223 /* Clear comphy selector - if it was already configured.
224 * (might be that this comphy was configured as PCIe/USB,
225 * in such case, no need to clear comphy selector because PCIe/USB
226 * are controlled by hpipe selector).
227 */
228 if (field) {
229 reg &= ~mask;
230 mmio_write_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET,
231 reg);
232 }
233}
234
235/* PHY selector configures SATA and Network modes */
236static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base,
237 uint8_t comphy_index, uint32_t comphy_mode)
238{
239 uint32_t reg, mask;
240 uint32_t comphy_offset =
241 COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index;
242 int mode;
243
244 /* If phy selector is used the pipe selector should be marked as
245 * unconnected.
246 */
247 mvebu_cp110_comphy_clr_pipe_selector(comphy_base, comphy_index);
248
249 /* Comphy mode (compound of the IO mode and id). Here, only the IO mode
250 * is required to distinguish between SATA and network modes.
251 */
252 mode = COMPHY_GET_MODE(comphy_mode);
253
254 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset;
255 reg = mmio_read_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET);
256 reg &= ~mask;
257
258 /* SATA port 0/1 require the same configuration */
259 if (mode == COMPHY_SATA_MODE) {
260 /* SATA selector values is always 4 */
261 reg |= COMMON_SELECTOR_COMPHYN_SATA << comphy_offset;
262 } else {
263 switch (comphy_index) {
264 case(0):
265 case(1):
266 case(2):
267 /* For comphy 0,1, and 2:
268 * Network selector value is always 1.
269 */
270 reg |= COMMON_SELECTOR_COMPHY0_1_2_NETWORK <<
271 comphy_offset;
272 break;
273 case(3):
274 /* For comphy 3:
275 * 0x1 = RXAUI_Lane1
276 * 0x2 = SGMII/HS-SGMII Port1
277 */
278 if (mode == COMPHY_RXAUI_MODE)
279 reg |= COMMON_SELECTOR_COMPHY3_RXAUI <<
280 comphy_offset;
281 else
282 reg |= COMMON_SELECTOR_COMPHY3_SGMII <<
283 comphy_offset;
284 break;
285 case(4):
286 /* For comphy 4:
287 * 0x1 = SGMII/HS-SGMII Port1, XFI1/SFI1
288 * 0x2 = SGMII/HS-SGMII Port0: XFI0/SFI0, RXAUI_Lane0
289 *
290 * We want to check if SGMII1/HS_SGMII1 is the
291 * requested mode in order to determine which value
292 * should be set (all other modes use the same value)
293 * so we need to strip the mode, and check the ID
294 * because we might handle SGMII0/HS_SGMII0 too.
295 */
296 /* TODO: need to distinguish between CP110 and CP115
297 * as SFI1/XFI1 available only for CP115.
298 */
299 if ((mode == COMPHY_SGMII_MODE ||
300 mode == COMPHY_HS_SGMII_MODE ||
301 mode == COMPHY_SFI_MODE) &&
302 COMPHY_GET_ID(comphy_mode) == 1)
303 reg |= COMMON_SELECTOR_COMPHY4_PORT1 <<
304 comphy_offset;
305 else
306 reg |= COMMON_SELECTOR_COMPHY4_ALL_OTHERS <<
307 comphy_offset;
308 break;
309 case(5):
310 /* For comphy 5:
311 * 0x1 = SGMII/HS-SGMII Port2
312 * 0x2 = RXAUI Lane1
313 */
314 if (mode == COMPHY_RXAUI_MODE)
315 reg |= COMMON_SELECTOR_COMPHY5_RXAUI <<
316 comphy_offset;
317 else
318 reg |= COMMON_SELECTOR_COMPHY5_SGMII <<
319 comphy_offset;
320 break;
321 }
322 }
323
324 mmio_write_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET, reg);
325}
326
327/* PIPE selector configures for PCIe, USB 3.0 Host, and USB 3.0 Device mode */
328static void mvebu_cp110_comphy_set_pipe_selector(uint64_t comphy_base,
329 uint8_t comphy_index, uint32_t comphy_mode)
330{
331 uint32_t reg;
332 uint32_t shift = COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index;
333 int mode = COMPHY_GET_MODE(comphy_mode);
334 uint32_t mask = COMMON_SELECTOR_COMPHY_MASK << shift;
335 uint32_t pipe_sel = 0x0;
336
337 /* If pipe selector is used the phy selector should be marked as
338 * unconnected.
339 */
340 mvebu_cp110_comphy_clr_phy_selector(comphy_base, comphy_index);
341
342 reg = mmio_read_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET);
343 reg &= ~mask;
344
345 switch (mode) {
346 case (COMPHY_PCIE_MODE):
347 /* For lanes support PCIE, selector value are all same */
348 pipe_sel = COMMON_SELECTOR_PIPE_COMPHY_PCIE;
349 break;
350
351 case (COMPHY_USB3H_MODE):
352 /* Only lane 1-4 support USB host, selector value is same */
353 if (comphy_index == COMPHY_LANE0 ||
354 comphy_index == COMPHY_LANE5)
355 ERROR("COMPHY[%d] mode[%d] is invalid\n",
356 comphy_index, mode);
357 else
358 pipe_sel = COMMON_SELECTOR_PIPE_COMPHY_USBH;
359 break;
360
361 case (COMPHY_USB3D_MODE):
362 /* Lane 1 and 4 support USB device, selector value is same */
363 if (comphy_index == COMPHY_LANE1 ||
364 comphy_index == COMPHY_LANE4)
365 pipe_sel = COMMON_SELECTOR_PIPE_COMPHY_USBD;
366 else
367 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index,
368 mode);
369 break;
370
371 default:
372 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode);
373 break;
374 }
375
376 mmio_write_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET, reg |
377 (pipe_sel << shift));
378}
379
380int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, uint8_t comphy_index)
381{
382 uintptr_t sd_ip_addr, addr;
383 uint32_t mask, data;
384 int ret = 0;
385
386 debug_enter();
387
388 sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
389 comphy_index);
390
391 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
392 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK &
393 SD_EXTERNAL_STATUS0_PLL_RX_MASK;
394 mask = data;
395 data = polling_with_timeout(addr, data, mask,
396 PLL_LOCK_TIMEOUT, REG_32BIT);
397 if (data != 0) {
398 if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)
399 ERROR("RX PLL is not locked\n");
400 if (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)
401 ERROR("TX PLL is not locked\n");
402
403 ret = -ETIMEDOUT;
404 }
405
406 debug_exit();
407
408 return ret;
409}
410
411static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
412 uint8_t comphy_index, uint32_t comphy_mode)
413{
414 uintptr_t hpipe_addr, sd_ip_addr, comphy_addr;
415 uint32_t mask, data;
416 int ret = 0;
417
418 debug_enter();
419
420 /* configure phy selector for SATA */
421 mvebu_cp110_comphy_set_phy_selector(comphy_base,
422 comphy_index, comphy_mode);
423
424 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
425 comphy_index);
426 sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
427 comphy_index);
428 comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
429
430 debug(" add hpipe 0x%lx, sd 0x%lx, comphy 0x%lx\n",
431 hpipe_addr, sd_ip_addr, comphy_addr);
432 debug("stage: RFU configurations - hard reset comphy\n");
433 /* RFU configurations - hard reset comphy */
434 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
435 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
436 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
437 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
438 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
439 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
440 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
441 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
442 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
443
444 /* Set select data width 40Bit - SATA mode only */
445 reg_set(comphy_addr + COMMON_PHY_CFG6_REG,
446 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET,
447 COMMON_PHY_CFG6_IF_40_SEL_MASK);
448
449 /* release from hard reset in SD external */
450 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
451 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
452 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
453 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
454 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
455
456 /* Wait 1ms - until band gap and ref clock ready */
457 mdelay(1);
458
459 debug("stage: Comphy configuration\n");
460 /* Start comphy Configuration */
461 /* Set reference clock to comes from group 1 - choose 25Mhz */
462 reg_set(hpipe_addr + HPIPE_MISC_REG,
463 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
464 HPIPE_MISC_REFCLK_SEL_MASK);
465 /* Reference frequency select set 1 (for SATA = 25Mhz) */
466 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
467 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
468 /* PHY mode select (set SATA = 0x0 */
469 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
470 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
471 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
472 /* Set max PHY generation setting - 6Gbps */
473 reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
474 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
475 HPIPE_INTERFACE_GEN_MAX_MASK);
476 /* Set select data width 40Bit (SEL_BITS[2:0]) */
477 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
478 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
479
480 debug("stage: Analog parameters from ETP(HW)\n");
481 /* G1 settings */
482 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
483 data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +0200484 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
485 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300486 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
487 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
488 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
489 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
490 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
491 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
492 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
493
494 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
495 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
496 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
497 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
498 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
499 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
500 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK;
501 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET;
502 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK;
503 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET;
504 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
505
506 /* G2 settings */
507 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
508 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +0200509 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
510 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300511 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
512 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
513 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
514 data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET;
515 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK;
516 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET;
517 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
518
519 /* G3 settings */
520 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
521 data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
522 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
523 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
524 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK;
525 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET;
526 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK;
527 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET;
528 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK;
529 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET;
530 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK;
531 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET;
532 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
533 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
534 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
535
536 /* DTL Control */
537 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK;
538 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET;
539 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK;
540 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET;
541 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
542 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
543 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK;
544 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET;
545 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK;
546 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET;
547 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK;
548 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET;
549 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
550 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET;
551 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
552
553 /* Trigger sampler enable pulse */
554 mask = HPIPE_SMAPLER_MASK;
555 data = 0x1 << HPIPE_SMAPLER_OFFSET;
556 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
557 mask = HPIPE_SMAPLER_MASK;
558 data = 0x0 << HPIPE_SMAPLER_OFFSET;
559 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
560
561 /* VDD Calibration Control 3 */
562 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
563 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
564 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
565
566 /* DFE Resolution Control */
567 mask = HPIPE_DFE_RES_FORCE_MASK;
568 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
569 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
570
571 /* DFE F3-F5 Coefficient Control */
572 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
573 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
574 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
575 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
576 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
577
578 /* G3 Setting 3 */
579 mask = HPIPE_G3_FFE_CAP_SEL_MASK;
580 data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET;
581 mask |= HPIPE_G3_FFE_RES_SEL_MASK;
582 data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET;
583 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK;
584 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET;
585 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
586 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
587 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
588 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
589 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
590
591 /* G3 Setting 4 */
592 mask = HPIPE_G3_DFE_RES_MASK;
593 data = 0x1 << HPIPE_G3_DFE_RES_OFFSET;
594 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
595
596 /* Offset Phase Control */
597 mask = HPIPE_OS_PH_OFFSET_MASK;
598 data = 0x61 << HPIPE_OS_PH_OFFSET_OFFSET;
599 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK;
600 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET;
601 mask |= HPIPE_OS_PH_VALID_MASK;
602 data |= 0x0 << HPIPE_OS_PH_VALID_OFFSET;
603 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
604 mask = HPIPE_OS_PH_VALID_MASK;
605 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET;
606 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
607 mask = HPIPE_OS_PH_VALID_MASK;
608 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET;
609 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
610
611 /* Set G1 TX amplitude and TX post emphasis value */
612 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
613 data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
614 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
615 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET;
616 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
617 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
618 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
619 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET;
620 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
621
622 /* Set G2 TX amplitude and TX post emphasis value */
623 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK;
624 data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET;
625 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK;
626 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET;
627 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK;
628 data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET;
629 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK;
630 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET;
631 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask);
632
633 /* Set G3 TX amplitude and TX post emphasis value */
634 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK;
635 data = 0x1e << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET;
636 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK;
637 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET;
638 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK;
639 data |= 0xe << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET;
640 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK;
641 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET;
642 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK;
643 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET;
644 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK;
645 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET;
646 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask);
647
648 /* SERDES External Configuration 2 register */
649 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK;
650 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET;
651 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
652
653 /* DFE reset sequence */
654 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
655 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
656 HPIPE_PWR_CTR_RST_DFE_MASK);
657 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
658 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
659 HPIPE_PWR_CTR_RST_DFE_MASK);
660 /* SW reset for interrupt logic */
661 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
662 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
663 HPIPE_PWR_CTR_SFT_RST_MASK);
664 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
665 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
666 HPIPE_PWR_CTR_SFT_RST_MASK);
667
668 debug_exit();
669
670 return ret;
671}
672
673static int mvebu_cp110_comphy_sgmii_power_on(uint64_t comphy_base,
674 uint8_t comphy_index, uint32_t comphy_mode)
675{
676 uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
677 uint32_t mask, data, sgmii_speed = COMPHY_GET_SPEED(comphy_mode);
678 int ret = 0;
679
680 debug_enter();
681
682 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
683 comphy_index);
684 sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
685 comphy_index);
686 comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
687
688 /* configure phy selector for SGMII */
689 mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index,
690 comphy_mode);
691
692 /* Confiugre the lane */
693 debug("stage: RFU configurations - hard reset comphy\n");
694 /* RFU configurations - hard reset comphy */
695 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
696 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
697 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
698 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
699 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
700
701 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
702 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
703 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
704 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
705 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
706
707 if (sgmii_speed == COMPHY_SPEED_1_25G) {
708 /* SGMII 1G, SerDes speed 1.25G */
709 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
710 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
711 } else if (sgmii_speed == COMPHY_SPEED_3_125G) {
712 /* HS SGMII (2.5G), SerDes speed 3.125G */
713 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
714 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
715 } else {
716 /* Other rates are not supported */
717 ERROR("unsupported SGMII speed on comphy%d\n", comphy_index);
718 return -EINVAL;
719 }
720
721 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
722 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
723 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
724 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
725 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
726 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
727 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
728
729 /* Set hard reset */
730 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
731 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
732 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
733 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
734 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
735 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
736 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
737
738 /* Release hard reset */
739 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
740 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
741 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
742 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
743 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
744
745 /* Wait 1ms - until band gap and ref clock ready */
746 mdelay(1);
747
748 /* Make sure that 40 data bits is disabled
749 * This bit is not cleared by reset
750 */
751 mask = COMMON_PHY_CFG6_IF_40_SEL_MASK;
752 data = 0 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET;
753 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask);
754
755 /* Start comphy Configuration */
756 debug("stage: Comphy configuration\n");
757 /* set reference clock */
758 mask = HPIPE_MISC_REFCLK_SEL_MASK;
759 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
760 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
761 /* Power and PLL Control */
762 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
763 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
764 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
765 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
766 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
767 /* Loopback register */
768 mask = HPIPE_LOOPBACK_SEL_MASK;
769 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
770 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
771 /* rx control 1 */
772 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
773 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
774 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
775 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
776 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
777 /* DTL Control */
778 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
779 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
780 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
781
782 /* Set analog parameters from ETP(HW) - for now use the default datas */
783 debug("stage: Analog parameters from ETP(HW)\n");
784
785 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
786 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
787 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
788
789 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
790 /* SERDES External Configuration */
791 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
792 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
793 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
794 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
795 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
796 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
797 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
798
799 ret = mvebu_cp110_comphy_is_pll_locked(comphy_base, comphy_index);
800 if (ret)
801 return ret;
802
803 /* RX init */
804 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
805 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
806 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
807
808 /* check that RX init done */
809 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
810 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
811 mask = data;
812 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
813 if (data != 0) {
814 ERROR("RX init failed\n");
815 ret = -ETIMEDOUT;
816 }
817
818 debug("stage: RF Reset\n");
819 /* RF Reset */
820 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
821 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
822 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
823 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
824 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
825
826 debug_exit();
827
828 return ret;
829}
830
831static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
832 uint8_t comphy_index,
833 uint32_t comphy_mode)
834{
835 uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
836 uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode);
837 int ret = 0;
838
839 debug_enter();
840
841 if ((speed != COMPHY_SPEED_5_15625G) &&
842 (speed != COMPHY_SPEED_10_3125G) &&
843 (speed != COMPHY_SPEED_DEFAULT)) {
844 ERROR("comphy:%d: unsupported sfi/xfi speed\n", comphy_index);
845 return -EINVAL;
846 }
847
848 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
849 comphy_index);
850 sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
851 comphy_index);
852 comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
853
854 /* configure phy selector for XFI/SFI */
855 mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index,
856 comphy_mode);
857
858 debug("stage: RFU configurations - hard reset comphy\n");
859 /* RFU configurations - hard reset comphy */
860 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
861 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
862 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
863 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
864 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
865
866 /* Make sure that 40 data bits is disabled
867 * This bit is not cleared by reset
868 */
869 mask = COMMON_PHY_CFG6_IF_40_SEL_MASK;
870 data = 0 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET;
871 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask);
872
873 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
874 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
875 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
876 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
877 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
878 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
879 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
880 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
881 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
882 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
883 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
884 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
885 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
886 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
887
888 /* release from hard reset */
889 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
890 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
891 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
892 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
893 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
894 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
895 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
896
897 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
898 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
899 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
900 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
901 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
902
903 /* Wait 1ms - until band gap and ref clock ready */
904 mdelay(1);
905
906 /* Start comphy Configuration */
907 debug("stage: Comphy configuration\n");
908 /* set reference clock */
909 mask = HPIPE_MISC_ICP_FORCE_MASK;
910 data = (speed == COMPHY_SPEED_5_15625G) ?
911 (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) :
912 (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET);
913 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
914 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
915 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
916 /* Power and PLL Control */
917 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
918 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
919 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
920 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
921 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
922 /* Loopback register */
923 mask = HPIPE_LOOPBACK_SEL_MASK;
924 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
925 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
926 /* rx control 1 */
927 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
928 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
929 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
930 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
931 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
932 /* DTL Control */
933 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
934 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
935 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
936
937 /* Transmitter/Receiver Speed Divider Force */
938 if (speed == COMPHY_SPEED_5_15625G) {
939 mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK;
940 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET;
941 mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK;
942 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET;
943 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK;
944 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET;
945 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
946 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET;
947 } else {
948 mask = HPIPE_TXDIGCK_DIV_FORCE_MASK;
949 data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET;
950 }
951 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
952
953 /* Set analog parameters from ETP(HW) */
954 debug("stage: Analog parameters from ETP(HW)\n");
955 /* SERDES External Configuration 2 */
956 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK;
957 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET;
958 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
959 /* 0x7-DFE Resolution control */
960 mask = HPIPE_DFE_RES_FORCE_MASK;
961 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
962 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
963 /* 0xd-G1_Setting_0 */
964 if (speed == COMPHY_SPEED_5_15625G) {
965 mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
966 data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
967 } else {
968 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
969 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
970 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
971 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
972 }
973 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
974 /* Genration 1 setting 2 (G1_Setting_2) */
975 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
976 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET;
977 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK;
978 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET;
979 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
980 /* Transmitter Slew Rate Control register (tx_reg1) */
981 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK;
982 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET;
983 mask |= HPIPE_TX_REG1_SLC_EN_MASK;
984 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET;
985 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask);
986 /* Impedance Calibration Control register (cal_reg1) */
987 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK;
988 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
989 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK;
990 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET;
991 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask);
992 /* Generation 1 Setting 5 (g1_setting_5) */
993 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK;
994 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
995 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
996
997 /* 0xE-G1_Setting_1 */
998 mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
999 data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1000 if (speed == COMPHY_SPEED_5_15625G) {
1001 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1002 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +02001003 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
1004 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03001005 } else {
1006 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1007 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +02001008 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
1009 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03001010 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
1011 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
1012 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
1013 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
1014 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
1015 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
1016 }
1017 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1018
1019 /* 0xA-DFE_Reg3 */
1020 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1021 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1022 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1023 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1024 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1025
1026 /* 0x111-G1_Setting_4 */
1027 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1028 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1029 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1030 /* Genration 1 setting 3 (G1_Setting_3) */
1031 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK;
1032 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET;
1033 if (speed == COMPHY_SPEED_5_15625G) {
1034 /* Force FFE (Feed Forward Equalization) to 5G */
1035 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
1036 data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
1037 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
1038 data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
1039 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
1040 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
1041 }
1042 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1043
1044 /* Connfigure RX training timer */
1045 mask = HPIPE_RX_TRAIN_TIMER_MASK;
1046 data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET;
1047 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1048
1049 /* Enable TX train peak to peak hold */
1050 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
1051 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
1052 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1053
1054 /* Configure TX preset index */
1055 mask = HPIPE_TX_PRESET_INDEX_MASK;
1056 data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET;
1057 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask);
1058
1059 /* Disable pattern lock lost timeout */
1060 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
1061 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
1062 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1063
1064 /* Configure TX training pattern and TX training 16bit auto */
1065 mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK;
1066 data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET;
1067 mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK;
1068 data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET;
1069 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1070
1071 /* Configure Training patten number */
1072 mask = HPIPE_TRAIN_PAT_NUM_MASK;
1073 data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET;
1074 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask);
1075
1076 /* Configure differencial manchester encoter to ethernet mode */
1077 mask = HPIPE_DME_ETHERNET_MODE_MASK;
1078 data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET;
1079 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask);
1080
1081 /* Configure VDD Continuous Calibration */
1082 mask = HPIPE_CAL_VDD_CONT_MODE_MASK;
1083 data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET;
1084 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask);
1085
1086 /* Trigger sampler enable pulse (by toggleing the bit) */
1087 mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK;
1088 data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET;
1089 mask |= HPIPE_SMAPLER_MASK;
1090 data |= 0x1 << HPIPE_SMAPLER_OFFSET;
1091 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1092 mask = HPIPE_SMAPLER_MASK;
1093 data = 0x0 << HPIPE_SMAPLER_OFFSET;
1094 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1095
1096 /* Set External RX Regulator Control */
1097 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
1098 data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
1099 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1100
1101 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1102 /* SERDES External Configuration */
1103 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1104 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1105 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1106 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1107 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1108 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1109 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1110
1111 /* check PLL rx & tx ready */
1112 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1113 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1114 SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1115 mask = data;
1116 data = polling_with_timeout(addr, data, mask,
1117 PLL_LOCK_TIMEOUT, REG_32BIT);
1118 if (data != 0) {
1119 if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)
1120 ERROR("RX PLL is not locked\n");
1121 if (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)
1122 ERROR("TX PLL is not locked\n");
1123
1124 ret = -ETIMEDOUT;
1125 }
1126
1127 /* RX init */
1128 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1129 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1130 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1131
1132 /* check that RX init done */
1133 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1134 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1135 mask = data;
1136 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
1137 if (data != 0) {
1138 ERROR("RX init failed\n");
1139 ret = -ETIMEDOUT;
1140 }
1141
1142 debug("stage: RF Reset\n");
1143 /* RF Reset */
1144 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1145 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1146 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1147 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1148 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1149
1150 debug_exit();
1151
1152 return ret;
1153}
1154
1155static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base,
1156 uint8_t comphy_index, uint32_t comphy_mode)
1157{
1158 int ret = 0;
1159 uint32_t reg, mask, data, pcie_width;
1160 uint32_t clk_dir;
1161 uintptr_t hpipe_addr, comphy_addr, addr;
1162 _Bool clk_src = COMPHY_GET_CLK_SRC(comphy_mode);
1163
1164 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
1165 comphy_index);
1166 comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
1167 pcie_width = COMPHY_GET_PCIE_WIDTH(comphy_mode);
1168
1169 debug_enter();
1170
1171 spin_lock(&cp110_mac_reset_lock);
1172
1173 reg = mmio_read_32(SYS_CTRL_FROM_COMPHY_ADDR(comphy_base) +
1174 SYS_CTRL_UINIT_SOFT_RESET_REG);
1175 switch (comphy_index) {
1176 case COMPHY_LANE0:
1177 reg |= PCIE_MAC_RESET_MASK_PORT0;
1178 break;
1179 case COMPHY_LANE4:
1180 reg |= PCIE_MAC_RESET_MASK_PORT1;
1181 break;
1182 case COMPHY_LANE5:
1183 reg |= PCIE_MAC_RESET_MASK_PORT2;
1184 break;
1185 }
1186
1187 mmio_write_32(SYS_CTRL_FROM_COMPHY_ADDR(comphy_base) +
1188 SYS_CTRL_UINIT_SOFT_RESET_REG, reg);
1189 spin_unlock(&cp110_mac_reset_lock);
1190
1191 /* Configure PIPE selector for PCIE */
1192 mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index,
1193 comphy_mode);
1194
1195 /*
1196 * Read SAR (Sample-At-Reset) configuration for the PCIe clock
1197 * direction.
1198 *
1199 * SerDes Lane 4/5 got the PCIe ref-clock #1,
1200 * and SerDes Lane 0 got PCIe ref-clock #0
1201 */
1202 reg = mmio_read_32(DFX_FROM_COMPHY_ADDR(comphy_base) +
1203 SAR_STATUS_0_REG);
1204 if (comphy_index == COMPHY_LANE4 || comphy_index == COMPHY_LANE5)
1205 clk_dir = (reg & SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK) >>
1206 SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET;
1207 else
1208 clk_dir = (reg & SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK) >>
1209 SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET;
1210
1211 debug("On lane %d\n", comphy_index);
1212 debug("PCIe clock direction = %x\n", clk_dir);
1213 debug("PCIe Width = %d\n", pcie_width);
1214
1215 /* enable PCIe X4 and X2 */
1216 if (comphy_index == COMPHY_LANE0) {
1217 if (pcie_width == PCIE_LNK_X4) {
1218 data = 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET;
1219 mask = COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK;
1220 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1221 data, mask);
1222 } else if (pcie_width == PCIE_LNK_X2) {
1223 data = 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET;
1224 mask = COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK;
1225 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask);
1226 }
1227 }
1228
1229 /* If PCIe clock is output and clock source from SerDes lane 5,
1230 * need to configure the clock-source MUX.
1231 * By default, the clock source is from lane 4
1232 */
1233 if (clk_dir && clk_src && (comphy_index == COMPHY_LANE5)) {
1234 data = DFX_DEV_GEN_PCIE_CLK_SRC_MUX <<
1235 DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET;
1236 mask = DFX_DEV_GEN_PCIE_CLK_SRC_MASK;
1237 reg_set(DFX_FROM_COMPHY_ADDR(comphy_base) +
1238 DFX_DEV_GEN_CTRL12_REG, data, mask);
1239 }
1240
1241 debug("stage: RFU configurations - hard reset comphy\n");
1242 /* RFU configurations - hard reset comphy */
1243 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1244 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1245 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1246 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1247 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
1248 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
1249 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
1250 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
1251 mask |= COMMON_PHY_PHY_MODE_MASK;
1252 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
1253 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1254
1255 /* release from hard reset */
1256 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
1257 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
1258 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
1259 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
1260 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1261
1262 /* Wait 1ms - until band gap and ref clock ready */
1263 mdelay(1);
1264 /* Start comphy Configuration */
1265 debug("stage: Comphy configuration\n");
1266 /* Set PIPE soft reset */
1267 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
1268 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
1269 /* Set PHY datapath width mode for V0 */
1270 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
1271 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
1272 /* Set Data bus width USB mode for V0 */
1273 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
1274 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
1275 /* Set CORE_CLK output frequency for 250Mhz */
1276 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
1277 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
1278 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
1279 /* Set PLL ready delay for 0x2 */
1280 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
1281 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
1282 if (pcie_width != PCIE_LNK_X1) {
1283 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET;
1284 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK;
1285 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
1286 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
1287 }
1288 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
1289
1290 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */
1291 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
1292 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
1293 if (pcie_width != PCIE_LNK_X1) {
1294 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK;
1295 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK;
1296 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
1297 if (comphy_index == 0) {
1298 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET;
1299 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
1300 } else if (comphy_index == (pcie_width - 1)) {
1301 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
1302 }
1303 }
1304 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
1305 /* Config update polarity equalization */
1306 data = 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET;
1307 mask = HPIPE_CFG_UPDATE_POLARITY_MASK;
1308 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, data, mask);
1309 /* Set PIPE version 4 to mode enable */
1310 data = 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET;
1311 mask = HPIPE_DFE_CTRL_28_PIPE4_MASK;
1312 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, data, mask);
1313 /* TODO: check if pcie clock is output/input - for bringup use input*/
1314 /* Enable PIN clock 100M_125M */
1315 mask = 0;
1316 data = 0;
1317 /* Only if clock is output, configure the clock-source mux */
1318 if (clk_dir) {
1319 mask |= HPIPE_MISC_CLK100M_125M_MASK;
1320 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
1321 }
1322 /* Set PIN_TXDCLK_2X Clock Freq. Selection for outputs 500MHz clock */
1323 mask |= HPIPE_MISC_TXDCLK_2X_MASK;
1324 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
1325 /* Enable 500MHz Clock */
1326 mask |= HPIPE_MISC_CLK500_EN_MASK;
1327 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
1328 if (clk_dir) { /* output */
1329 /* Set reference clock comes from group 1 */
1330 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
1331 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
1332 } else {
1333 /* Set reference clock comes from group 2 */
1334 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
1335 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
1336 }
1337 mask |= HPIPE_MISC_ICP_FORCE_MASK;
1338 data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
1339 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
1340 if (clk_dir) { /* output */
1341 /* Set reference frequcency select - 0x2 for 25MHz*/
1342 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1343 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1344 } else {
1345 /* Set reference frequcency select - 0x0 for 100MHz*/
1346 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1347 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1348 }
1349 /* Set PHY mode to PCIe */
1350 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1351 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1352 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1353
1354 /* ref clock alignment */
1355 if (pcie_width != PCIE_LNK_X1) {
1356 mask = HPIPE_LANE_ALIGN_OFF_MASK;
1357 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET;
1358 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
1359 }
1360
1361 /* Set the amount of time spent in the LoZ state - set for 0x7 only if
1362 * the PCIe clock is output
1363 */
1364 if (clk_dir)
1365 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
1366 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
1367 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
1368
1369 /* Set Maximal PHY Generation Setting(8Gbps) */
1370 mask = HPIPE_INTERFACE_GEN_MAX_MASK;
1371 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
1372 /* Bypass frame detection and sync detection for RX DATA */
1373 mask |= HPIPE_INTERFACE_DET_BYPASS_MASK;
1374 data |= 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
1375 /* Set Link Train Mode (Tx training control pins are used) */
1376 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
1377 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
1378 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
1379
1380 /* Set Idle_sync enable */
1381 mask = HPIPE_PCIE_IDLE_SYNC_MASK;
1382 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
1383 /* Select bits for PCIE Gen3(32bit) */
1384 mask |= HPIPE_PCIE_SEL_BITS_MASK;
1385 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
1386 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
1387
1388 /* Enable Tx_adapt_g1 */
1389 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
1390 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
1391 /* Enable Tx_adapt_gn1 */
1392 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
1393 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
1394 /* Disable Tx_adapt_g0 */
1395 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
1396 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
1397 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
1398
1399 /* Set reg_tx_train_chk_init */
1400 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
1401 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
1402 /* Enable TX_COE_FM_PIN_PCIE3_EN */
1403 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
1404 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
1405 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1406
1407 debug("stage: TRx training parameters\n");
1408 /* Set Preset sweep configurations */
1409 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK;
1410 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET;
1411 mask |= HPIPE_TX_NUM_OF_PRESET_MASK;
1412 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET;
1413 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK;
1414 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET;
1415 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
1416
1417 /* Tx train start configuration */
1418 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK;
1419 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET;
1420 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK;
1421 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET;
1422 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK;
1423 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET;
1424 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
1425 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET;
1426 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1427
1428 /* Enable Tx train P2P */
1429 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
1430 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
1431 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1432
1433 /* Configure Tx train timeout */
1434 mask = HPIPE_TRX_TRAIN_TIMER_MASK;
1435 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET;
1436 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
1437
1438 /* Disable G0/G1/GN1 adaptation */
1439 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK
1440 | HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
1441 data = 0;
1442 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
1443
1444 /* Disable DTL frequency loop */
1445 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
1446 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
1447 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
1448
1449 /* Configure G3 DFE */
1450 mask = HPIPE_G3_DFE_RES_MASK;
1451 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
1452 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
1453
1454 /* Use TX/RX training result for DFE */
1455 mask = HPIPE_DFE_RES_FORCE_MASK;
1456 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
1457 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1458
1459 /* Configure initial and final coefficient value for receiver */
1460 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
1461 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
1462
1463 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
1464 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
1465
1466 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
1467 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
1468 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
1469
1470 /* Trigger sampler enable pulse */
1471 mask = HPIPE_SMAPLER_MASK;
1472 data = 0x1 << HPIPE_SMAPLER_OFFSET;
1473 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1474 udelay(5);
1475 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
1476
1477 /* FFE resistor tuning for different bandwidth */
1478 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
1479 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
1480 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
1481 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
1482 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
1483
1484 /* Pattern lock lost timeout disable */
1485 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
1486 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
1487 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1488
1489 /* Configure DFE adaptations */
1490 mask = HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK;
1491 data = 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET;
1492 mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
1493 data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
1494 mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
1495 data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
1496 mask |= HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
1497 data |= 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
1498 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
1499
1500 mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
1501 data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
1502 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
1503
1504 /* Genration 2 setting 1*/
1505 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
1506 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +02001507 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
1508 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03001509 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
1510 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
1511 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
1512
1513 /* DFE enable */
1514 mask = HPIPE_G2_DFE_RES_MASK;
1515 data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
1516 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
1517
1518 /* Configure DFE Resolution */
1519 mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
1520 data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
1521 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
1522
1523 /* VDD calibration control */
1524 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
1525 data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
1526 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1527
1528 /* Set PLL Charge-pump Current Control */
1529 mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
1530 data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
1531 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
1532
1533 /* Set lane rqualization remote setting */
1534 mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
1535 data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
1536 mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
1537 data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
1538 mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
1539 data |= 0x6 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
1540 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
1541
1542 mask = HPIPE_CFG_EQ_BUNDLE_DIS_MASK;
1543 data = 0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET;
1544 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG2_REG, data, mask);
1545
1546 debug("stage: Comphy power up\n");
1547
1548 /* For PCIe X4 or X2:
1549 * release from reset only after finish to configure all lanes
1550 */
1551 if ((pcie_width == PCIE_LNK_X1) || (comphy_index == (pcie_width - 1))) {
1552 uint32_t i, start_lane, end_lane;
1553
1554 if (pcie_width != PCIE_LNK_X1) {
1555 /* allows writing to all lanes in one write */
1556 data = 0x0;
1557 if (pcie_width == PCIE_LNK_X2)
1558 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK;
1559 else if (pcie_width == PCIE_LNK_X4)
1560 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK;
1561 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask);
1562 start_lane = 0;
1563 end_lane = pcie_width;
1564
1565 /* Release from PIPE soft reset
1566 * For PCIe by4 or by2:
1567 * release from soft reset all lanes - can't use
1568 * read modify write
1569 */
1570 reg_set(HPIPE_ADDR(
1571 COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), 0) +
1572 HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff);
1573 } else {
1574 start_lane = comphy_index;
1575 end_lane = comphy_index + 1;
1576
1577 /* Release from PIPE soft reset
1578 * for PCIe by4 or by2:
1579 * release from soft reset all lanes
1580 */
1581 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
1582 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
1583 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
1584 }
1585
1586 if (pcie_width != PCIE_LNK_X1) {
1587 /* disable writing to all lanes with one write */
1588 if (pcie_width == PCIE_LNK_X2) {
1589 data = (COMPHY_LANE0 <<
1590 COMMON_PHY_SD_CTRL1_COMPHY_0_PORT_OFFSET) |
1591 (COMPHY_LANE1 <<
1592 COMMON_PHY_SD_CTRL1_COMPHY_1_PORT_OFFSET);
1593 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK;
1594 } else if (pcie_width == PCIE_LNK_X4) {
1595 data = (COMPHY_LANE0 <<
1596 COMMON_PHY_SD_CTRL1_COMPHY_0_PORT_OFFSET) |
1597 (COMPHY_LANE1 <<
1598 COMMON_PHY_SD_CTRL1_COMPHY_1_PORT_OFFSET) |
1599 (COMPHY_LANE2 <<
1600 COMMON_PHY_SD_CTRL1_COMPHY_2_PORT_OFFSET) |
1601 (COMPHY_LANE3 <<
1602 COMMON_PHY_SD_CTRL1_COMPHY_3_PORT_OFFSET);
1603 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK;
1604 }
1605 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1606 data, mask);
1607 }
1608
1609 debug("stage: Check PLL\n");
1610 /* Read lane status */
1611 for (i = start_lane; i < end_lane; i++) {
1612 addr = HPIPE_ADDR(
1613 COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), i) +
1614 HPIPE_LANE_STATUS1_REG;
1615 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
1616 mask = data;
1617 ret = polling_with_timeout(addr, data, mask,
1618 PLL_LOCK_TIMEOUT,
1619 REG_32BIT);
1620 if (ret)
1621 ERROR("Failed to lock PCIE PLL\n");
1622 }
1623 }
1624
1625 debug_exit();
1626
1627 return ret;
1628}
1629
1630static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base,
1631 uint8_t comphy_index, uint32_t comphy_mode)
1632{
1633 uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
1634 uint32_t mask, data;
1635 int ret = 0;
1636
1637 debug_enter();
1638
1639 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
1640 comphy_index);
1641 comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
1642 sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
1643 comphy_index);
1644
1645 /* configure phy selector for RXAUI */
1646 mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index,
1647 comphy_mode);
1648
1649 /* RFU configurations - hard reset comphy */
1650 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1651 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1652 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1653 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1654 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1655
1656 if (comphy_index == 2) {
1657 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1658 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
1659 COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
1660 }
1661 if (comphy_index == 4) {
1662 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1663 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
1664 COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
1665 }
1666
1667 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
1668 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1669 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1670 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1671 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1672 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1673 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1674 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1675 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1676 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1677 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1678 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1679 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1680 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
1681 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
1682 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1683
1684 /* release from hard reset */
1685 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1686 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1687 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1688 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1689 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1690 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1691 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1692
1693 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1694 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1695 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1696 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1697 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1698
1699 /* Wait 1ms - until band gap and ref clock ready */
1700 mdelay(1);
1701
1702 /* Start comphy Configuration */
1703 debug("stage: Comphy configuration\n");
1704 /* set reference clock */
1705 reg_set(hpipe_addr + HPIPE_MISC_REG,
1706 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
1707 HPIPE_MISC_REFCLK_SEL_MASK);
1708 /* Power and PLL Control */
1709 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1710 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1711 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1712 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1713 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1714 /* Loopback register */
1715 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
1716 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
1717 /* rx control 1 */
1718 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1719 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1720 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1721 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1722 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1723 /* DTL Control */
1724 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
1725 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
1726 HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
1727
1728 /* Set analog parameters from ETP(HW) */
1729 debug("stage: Analog parameters from ETP(HW)\n");
1730 /* SERDES External Configuration 2 */
1731 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
1732 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
1733 SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
1734 /* 0x7-DFE Resolution control */
1735 reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
1736 HPIPE_DFE_RES_FORCE_MASK);
1737 /* 0xd-G1_Setting_0 */
1738 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
1739 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
1740 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
1741 /* 0xE-G1_Setting_1 */
1742 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1743 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +02001744 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
1745 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03001746 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1747 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1748 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1749 /* 0xA-DFE_Reg3 */
1750 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1751 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1752 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1753 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1754 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1755
1756 /* 0x111-G1_Setting_4 */
1757 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1758 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1759 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1760
1761 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1762 /* SERDES External Configuration */
1763 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1764 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1765 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1766 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1767 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1768 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1769 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1770
1771
1772 /* check PLL rx & tx ready */
1773 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1774 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1775 SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1776 mask = data;
1777 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT);
1778 if (data != 0) {
1779 debug("Read from reg = %lx - value = 0x%x\n",
1780 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1781 ERROR("SD_EXTERNAL_STATUS0_PLL_RX is %d, -\"-_PLL_TX is %d\n",
1782 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1783 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1784 ret = -ETIMEDOUT;
1785 }
1786
1787 /* RX init */
1788 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
1789 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
1790 SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
1791
1792 /* check that RX init done */
1793 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1794 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1795 mask = data;
1796 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
1797 if (data != 0) {
1798 debug("Read from reg = %lx - value = 0x%x\n",
1799 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1800 ERROR("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1801 ret = -ETIMEDOUT;
1802 }
1803
1804 debug("stage: RF Reset\n");
1805 /* RF Reset */
1806 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1807 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1808 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1809 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1810 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1811
1812 debug_exit();
1813
1814 return ret;
1815}
1816
1817static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
1818 uint8_t comphy_index, uint32_t comphy_mode)
1819{
1820 uintptr_t hpipe_addr, comphy_addr, addr;
1821 uint32_t mask, data;
1822 int ret = 0;
1823
1824 debug_enter();
1825
1826 /* Configure PIPE selector for USB3 */
1827 mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index,
1828 comphy_mode);
1829
1830 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
1831 comphy_index);
1832 comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
1833
1834 debug("stage: RFU configurations - hard reset comphy\n");
1835 /* RFU configurations - hard reset comphy */
1836 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1837 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1838 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1839 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1840 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
1841 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
1842 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
1843 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
1844 mask |= COMMON_PHY_PHY_MODE_MASK;
1845 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
1846 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1847
1848 /* release from hard reset */
1849 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
1850 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
1851 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
1852 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
1853 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1854
1855 /* Wait 1ms - until band gap and ref clock ready */
1856 mdelay(1);
1857
1858 /* Start comphy Configuration */
1859 debug("stage: Comphy configuration\n");
1860 /* Set PIPE soft reset */
1861 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
1862 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
1863 /* Set PHY datapath width mode for V0 */
1864 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
1865 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
1866 /* Set Data bus width USB mode for V0 */
1867 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
1868 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
1869 /* Set CORE_CLK output frequency for 250Mhz */
1870 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
1871 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
1872 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
1873 /* Set PLL ready delay for 0x2 */
1874 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
1875 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
1876 HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
1877 /* Set reference clock to come from group 1 - 25Mhz */
1878 reg_set(hpipe_addr + HPIPE_MISC_REG,
1879 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
1880 HPIPE_MISC_REFCLK_SEL_MASK);
1881 /* Set reference frequcency select - 0x2 */
1882 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1883 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1884 /* Set PHY mode to USB - 0x5 */
1885 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1886 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1887 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1888 /* Set the amount of time spent in the LoZ state - set for 0x7 */
1889 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
1890 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
1891 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
1892 /* Set max PHY generation setting - 5Gbps */
1893 reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
1894 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
1895 HPIPE_INTERFACE_GEN_MAX_MASK);
1896 /* Set select data width 20Bit (SEL_BITS[2:0]) */
1897 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
1898 0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
1899 HPIPE_LOOPBACK_SEL_MASK);
1900 /* select de-emphasize 3.5db */
1901 reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
1902 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
1903 HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
1904 /* override tx margining from the MAC */
1905 reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
1906 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
1907 HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
1908
1909 /* Start analog parameters from ETP(HW) */
1910 debug("stage: Analog parameters from ETP(HW)\n");
1911 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
1912 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
1913 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
1914 /* Set Override PHY DFE control pins for 0x1 */
1915 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
1916 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
1917 /* Set Spread Spectrum Clock Enable fot 0x1 */
1918 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
1919 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
1920 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
1921 /* Confifure SSC amplitude */
1922 mask = HPIPE_G2_TX_SSC_AMP_MASK;
1923 data = 0x1f << HPIPE_G2_TX_SSC_AMP_OFFSET;
1924 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);
1925 /* End of analog parameters */
1926
1927 debug("stage: Comphy power up\n");
1928 /* Release from PIPE soft reset */
1929 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
1930 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
1931 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
1932
1933 /* wait 15ms - for comphy calibration done */
1934 debug("stage: Check PLL\n");
1935 /* Read lane status */
1936 addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
1937 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
1938 mask = data;
1939 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT);
1940 if (data != 0) {
1941 debug("Read from reg = %lx - value = 0x%x\n",
1942 hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
1943 ERROR("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
1944 ret = -ETIMEDOUT;
1945 }
1946
1947 debug_exit();
1948
1949 return ret;
1950}
1951
1952/* This function performs RX training for one Feed Forward Equalization (FFE)
1953 * value.
1954 * The RX traiing result is stored in 'Saved DFE values Register' (SAV_F0D).
1955 *
1956 * Return '0' on success, error code in a case of failure.
1957 */
1958static int mvebu_cp110_comphy_test_single_ffe(uint64_t comphy_base,
1959 uint8_t comphy_index,
1960 uint32_t ffe, uint32_t *result)
1961{
1962 uint32_t mask, data, timeout;
1963 uintptr_t hpipe_addr, sd_ip_addr;
1964
1965 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
1966 comphy_index);
1967
1968 sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
1969 comphy_index);
1970
1971 /* Configure PRBS counters */
1972 mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
1973 data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
1974 reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
1975
1976 mask = HPIPE_PHY_TEST_DATA_MASK;
1977 data = 0x64 << HPIPE_PHY_TEST_DATA_OFFSET;
1978 reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
1979
1980 mask = HPIPE_PHY_TEST_EN_MASK;
1981 data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
1982 reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
1983
1984 mdelay(50);
1985
1986 /* Set the FFE value */
1987 mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
1988 data = ffe << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
1989 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1990
1991 /* Start RX training */
1992 mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK;
1993 data = 1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET;
1994 reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask);
1995
1996 /* Check the result of RX training */
1997 timeout = RX_TRAINING_TIMEOUT;
1998 while (timeout) {
1999 data = mmio_read_32(sd_ip_addr + SD_EXTERNAL_STATAUS1_REG);
2000 if (data & SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_MASK)
2001 break;
2002 mdelay(1);
2003 timeout--;
2004 }
2005
2006 if (timeout == 0)
2007 return -ETIMEDOUT;
2008
2009 if (data & SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_MASK)
2010 return -EINVAL;
2011
2012 /* Stop RX training */
2013 mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK;
2014 data = 0 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET;
2015 reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask);
2016
2017 /* Read the result */
2018 data = mmio_read_32(hpipe_addr + HPIPE_SAVED_DFE_VALUES_REG);
2019 data &= HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK;
2020 data >>= HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET;
2021 *result = data;
2022
2023 mask = HPIPE_PHY_TEST_RESET_MASK;
2024 data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET;
2025 mask |= HPIPE_PHY_TEST_EN_MASK;
2026 data |= 0x0 << HPIPE_PHY_TEST_EN_OFFSET;
2027 reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
2028
2029 mask = HPIPE_PHY_TEST_RESET_MASK;
2030 data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET;
2031 reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
2032
2033 return 0;
2034}
2035
2036/* This function runs complete RX training sequence:
2037 * - Run RX training for all possible Feed Forward Equalization values
2038 * - Choose the FFE which gives the best result.
2039 * - Run RX training again with the best result.
2040 *
2041 * Return '0' on success, error code in a case of failure.
2042 */
2043int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
2044 uint8_t comphy_index)
2045{
2046 uint32_t mask, data, max_rx_train = 0, max_rx_train_index = 0;
2047 uintptr_t hpipe_addr;
2048 uint32_t rx_train_result;
2049 int ret, i;
2050
2051 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
2052 comphy_index);
2053
2054 debug_enter();
2055
2056 /* Configure SQ threshold and CDR lock */
2057 mask = HPIPE_SQUELCH_THRESH_IN_MASK;
2058 data = 0xc << HPIPE_SQUELCH_THRESH_IN_OFFSET;
2059 reg_set(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG, data, mask);
2060
2061 mask = HPIPE_SQ_DEGLITCH_WIDTH_P_MASK;
2062 data = 0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET;
2063 mask |= HPIPE_SQ_DEGLITCH_WIDTH_N_MASK;
2064 data |= 0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET;
2065 mask |= HPIPE_SQ_DEGLITCH_EN_MASK;
2066 data |= 0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET;
2067 reg_set(hpipe_addr + HPIPE_SQ_GLITCH_FILTER_CTRL, data, mask);
2068
2069 mask = HPIPE_CDR_LOCK_DET_EN_MASK;
2070 data = 0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET;
2071 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
2072
2073 udelay(100);
2074
2075 /* Determine if we have a cable attached to this comphy, if not,
2076 * we can't perform RX training.
2077 */
2078 data = mmio_read_32(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG);
2079 if (data & HPIPE_SQUELCH_DETECTED_MASK) {
2080 ERROR("Squelsh is not detected, can't perform RX training\n");
2081 return -EINVAL;
2082 }
2083
2084 data = mmio_read_32(hpipe_addr + HPIPE_LOOPBACK_REG);
2085 if (!(data & HPIPE_CDR_LOCK_MASK)) {
2086 ERROR("CDR is not locked, can't perform RX training\n");
2087 return -EINVAL;
2088 }
2089
2090 /* Do preparations for RX training */
2091 mask = HPIPE_DFE_RES_FORCE_MASK;
2092 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
2093 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
2094
2095 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
2096 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
2097 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
2098 data |= 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
2099 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2100
2101 /* Perform RX training for all possible FFE (Feed Forward
2102 * Equalization, possible values are 0-7).
2103 * We update the best value reached and the FFE which gave this value.
2104 */
2105 for (i = 0; i < MAX_NUM_OF_FFE; i++) {
2106 rx_train_result = 0;
2107 ret = mvebu_cp110_comphy_test_single_ffe(comphy_base,
2108 comphy_index, i,
2109 &rx_train_result);
2110
2111 if ((!ret) && (rx_train_result > max_rx_train)) {
2112 max_rx_train = rx_train_result;
2113 max_rx_train_index = i;
2114 }
2115 }
2116
2117 /* If we were able to determine which FFE gives the best value,
2118 * now we need to set it and run RX training again (only for this
2119 * FFE).
2120 */
2121 if (max_rx_train) {
2122 ret = mvebu_cp110_comphy_test_single_ffe(comphy_base,
2123 comphy_index,
2124 max_rx_train_index,
2125 &rx_train_result);
2126
2127 if (ret == 0)
2128 debug("RX Training passed (FFE = %d, result = 0x%x)\n",
2129 max_rx_train_index, rx_train_result);
2130 } else {
2131 ERROR("RX Training failed for comphy%d\n", comphy_index);
2132 ret = -EINVAL;
2133 }
2134
2135 debug_exit();
2136
2137 return ret;
2138}
2139
2140/* During AP the proper mode is auto-negotiated and the mac, pcs and serdes
2141 * configuration are done by the firmware loaded to the MG's CM3 for appropriate
2142 * negotiated mode. Therefore there is no need to configure the mac, pcs and
2143 * serdes from u-boot. The only thing that need to be setup is powering up
2144 * the comphy, which is done through Common PHY<n> Configuration 1 Register
2145 * (CP0: 0xF2441000, CP1: 0xF4441000). This step can't be done by MG's CM3,
2146 * since it doesn't have an access to this register-set (but it has access to
2147 * the network registers like: MG, AP, MAC, PCS, Serdes etc.)
2148 */
2149static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base,
2150 uint8_t comphy_index)
2151{
2152 uint32_t mask, data;
2153 uintptr_t comphy_addr = comphy_addr =
2154 COMPHY_ADDR(comphy_base, comphy_index);
2155
2156 debug_enter();
2157 debug("stage: RFU configurations - hard reset comphy\n");
2158 /* RFU configurations - hard reset comphy */
2159 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
2160 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
2161 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
2162 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
2163 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
2164 debug_exit();
2165
2166 return 0;
2167}
2168
2169/*
2170 * This function allows to reset the digital synchronizers between
2171 * the MAC and the PHY, it is required when the MAC changes its state.
2172 */
2173int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base,
2174 uint8_t comphy_index,
2175 uint32_t comphy_mode, uint32_t command)
2176{
2177 int mode = COMPHY_GET_MODE(comphy_mode);
2178 uintptr_t sd_ip_addr;
2179 uint32_t mask, data;
2180
2181 sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
2182 comphy_index);
2183
2184 switch (mode) {
2185 case (COMPHY_SGMII_MODE):
2186 case (COMPHY_HS_SGMII_MODE):
2187 case (COMPHY_XFI_MODE):
2188 case (COMPHY_SFI_MODE):
2189 case (COMPHY_RXAUI_MODE):
2190 mask = SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
2191 data = ((command == COMPHY_COMMAND_DIGITAL_PWR_OFF) ?
2192 0x0 : 0x1) << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
2193 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
2194 break;
2195 default:
2196 ERROR("comphy%d: Digital PWR ON/OFF is not supported\n",
2197 comphy_index);
2198 return -EINVAL;
2199 }
2200
2201 return 0;
2202}
2203
Grzegorz Jaszczyk4cff3082018-07-12 07:40:34 +02002204int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03002205 uint64_t comphy_mode)
2206{
2207 int mode = COMPHY_GET_MODE(comphy_mode);
2208 int err = 0;
2209
2210 debug_enter();
2211
2212 switch (mode) {
2213 case(COMPHY_SATA_MODE):
2214 err = mvebu_cp110_comphy_sata_power_on(comphy_base,
2215 comphy_index,
2216 comphy_mode);
2217 break;
2218 case(COMPHY_SGMII_MODE):
2219 case(COMPHY_HS_SGMII_MODE):
2220 err = mvebu_cp110_comphy_sgmii_power_on(comphy_base,
2221 comphy_index,
2222 comphy_mode);
2223 break;
2224 /* From comphy perspective, XFI and SFI are the same */
2225 case (COMPHY_XFI_MODE):
2226 case (COMPHY_SFI_MODE):
2227 err = mvebu_cp110_comphy_xfi_power_on(comphy_base,
2228 comphy_index,
2229 comphy_mode);
2230 break;
2231 case (COMPHY_PCIE_MODE):
2232 err = mvebu_cp110_comphy_pcie_power_on(comphy_base,
2233 comphy_index,
2234 comphy_mode);
2235 break;
2236 case (COMPHY_RXAUI_MODE):
2237 err = mvebu_cp110_comphy_rxaui_power_on(comphy_base,
2238 comphy_index,
2239 comphy_mode);
2240 case (COMPHY_USB3H_MODE):
2241 case (COMPHY_USB3D_MODE):
2242 err = mvebu_cp110_comphy_usb3_power_on(comphy_base,
2243 comphy_index,
2244 comphy_mode);
2245 break;
2246 case (COMPHY_AP_MODE):
2247 err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index);
2248 break;
2249 default:
Grzegorz Jaszczyk4cff3082018-07-12 07:40:34 +02002250 ERROR("comphy%d: unsupported comphy mode\n", comphy_index);
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03002251 err = -EINVAL;
2252 break;
2253 }
2254
2255 debug_exit();
2256
2257 return err;
2258}
2259
Grzegorz Jaszczyk4cff3082018-07-12 07:40:34 +02002260int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint8_t comphy_index)
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03002261{
2262 uintptr_t sd_ip_addr, comphy_ip_addr;
2263 uint32_t mask, data;
2264
2265 debug_enter();
2266
2267 sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
2268 comphy_index);
2269 comphy_ip_addr = COMPHY_ADDR(comphy_base, comphy_index);
2270
2271 /* Hard reset the comphy, for Ethernet modes and Sata */
2272 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
2273 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
2274 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
2275 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
2276 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
2277 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
2278 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
2279
2280 /* PCIe reset */
2281 spin_lock(&cp110_mac_reset_lock);
2282
2283 /* The mvebu_cp110_comphy_power_off will be called only from Linux (to
2284 * override settings done by bootloader) and it will be relevant only
2285 * to PCIe (called before check if to skip pcie power off or not).
2286 */
2287 data = mmio_read_32(SYS_CTRL_FROM_COMPHY_ADDR(comphy_base) +
2288 SYS_CTRL_UINIT_SOFT_RESET_REG);
2289 switch (comphy_index) {
2290 case COMPHY_LANE0:
2291 data &= ~PCIE_MAC_RESET_MASK_PORT0;
2292 break;
2293 case COMPHY_LANE4:
2294 data &= ~PCIE_MAC_RESET_MASK_PORT1;
2295 break;
2296 case COMPHY_LANE5:
2297 data &= ~PCIE_MAC_RESET_MASK_PORT2;
2298 break;
2299 }
2300
2301 mmio_write_32(SYS_CTRL_FROM_COMPHY_ADDR(comphy_base) +
2302 SYS_CTRL_UINIT_SOFT_RESET_REG, data);
2303 spin_unlock(&cp110_mac_reset_lock);
2304
2305 /* Hard reset the comphy, for PCIe and usb3 */
2306 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
2307 data = 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
2308 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
2309 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
2310 reg_set(comphy_ip_addr + COMMON_PHY_CFG1_REG, data, mask);
2311
2312 /* Clear comphy PHY and PIPE selector, can't rely on previous config. */
2313 mvebu_cp110_comphy_clr_phy_selector(comphy_base, comphy_index);
2314 mvebu_cp110_comphy_clr_pipe_selector(comphy_base, comphy_index);
2315
2316 debug_exit();
2317
2318 return 0;
2319}