Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
Juan Castillo | a08a5e7 | 2015-05-19 11:54:12 +0100 | [diff] [blame] | 34 | #include <auth_mod.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 35 | #include <bl_common.h> |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 36 | #include <debug.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 37 | #include <platform.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 38 | #include <platform_def.h> |
Dan Handley | bcd60ba | 2014-04-17 18:53:42 +0100 | [diff] [blame] | 39 | #include "bl1_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 42 | * Runs BL2 from the given entry point. It results in dropping the |
| 43 | * exception level |
| 44 | ******************************************************************************/ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 45 | static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep) |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 46 | { |
| 47 | bl1_arch_next_el_setup(); |
| 48 | |
| 49 | /* Tell next EL what we want done */ |
| 50 | bl2_ep->args.arg0 = RUN_IMAGE; |
| 51 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 52 | if (GET_SECURITY_STATE(bl2_ep->h.attr) == NON_SECURE) |
| 53 | change_security_state(GET_SECURITY_STATE(bl2_ep->h.attr)); |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 54 | |
| 55 | write_spsr_el3(bl2_ep->spsr); |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 56 | write_elr_el3(bl2_ep->pc); |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 57 | |
| 58 | eret(bl2_ep->args.arg0, |
| 59 | bl2_ep->args.arg1, |
| 60 | bl2_ep->args.arg2, |
| 61 | bl2_ep->args.arg3, |
| 62 | bl2_ep->args.arg4, |
| 63 | bl2_ep->args.arg5, |
| 64 | bl2_ep->args.arg6, |
| 65 | bl2_ep->args.arg7); |
| 66 | } |
| 67 | |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 68 | /******************************************************************************* |
| 69 | * The next function has a weak definition. Platform specific code can override |
| 70 | * it if it wishes to. |
| 71 | ******************************************************************************/ |
| 72 | #pragma weak bl1_init_bl2_mem_layout |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 73 | |
| 74 | /******************************************************************************* |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 75 | * Function that takes a memory layout into which BL2 has been loaded and |
| 76 | * populates a new memory layout for BL2 that ensures that BL1's data sections |
| 77 | * resident in secure RAM are not visible to BL2. |
| 78 | ******************************************************************************/ |
| 79 | void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, |
| 80 | meminfo_t *bl2_mem_layout) |
| 81 | { |
| 82 | const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; |
| 83 | |
| 84 | assert(bl1_mem_layout != NULL); |
| 85 | assert(bl2_mem_layout != NULL); |
| 86 | |
| 87 | /* Check that BL1's memory is lying outside of the free memory */ |
| 88 | assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || |
| 89 | (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size)); |
| 90 | |
| 91 | /* Remove BL1 RW data from the scope of memory visible to BL2 */ |
| 92 | *bl2_mem_layout = *bl1_mem_layout; |
| 93 | reserve_mem(&bl2_mem_layout->total_base, |
| 94 | &bl2_mem_layout->total_size, |
| 95 | BL1_RAM_BASE, |
| 96 | bl1_size); |
| 97 | |
| 98 | flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); |
| 99 | } |
| 100 | |
| 101 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 102 | * Function to perform late architectural and platform specific initialization. |
| 103 | * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only |
| 104 | * called by the primary cpu after a cold boot. |
| 105 | * TODO: Add support for alternative image load mechanism e.g using virtio/elf |
| 106 | * loader etc. |
| 107 | ******************************************************************************/ |
| 108 | void bl1_main(void) |
| 109 | { |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 110 | /* Announce our arrival */ |
| 111 | NOTICE(FIRMWARE_WELCOME_STR); |
| 112 | NOTICE("BL1: %s\n", version_string); |
| 113 | NOTICE("BL1: %s\n", build_message); |
| 114 | |
| 115 | INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT); |
| 116 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 117 | image_info_t bl2_image_info = { {0} }; |
| 118 | entry_point_info_t bl2_ep = { {0} }; |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 119 | meminfo_t *bl1_tzram_layout; |
| 120 | meminfo_t *bl2_tzram_layout = 0x0; |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 121 | int err; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 122 | |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 123 | #if DEBUG |
| 124 | unsigned long val; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 125 | /* |
| 126 | * Ensure that MMU/Caches and coherency are turned on |
| 127 | */ |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 128 | val = read_sctlr_el3(); |
Andrew Thoelke | 5e287b5 | 2015-06-11 14:12:14 +0100 | [diff] [blame] | 129 | assert(val & SCTLR_M_BIT); |
| 130 | assert(val & SCTLR_C_BIT); |
| 131 | assert(val & SCTLR_I_BIT); |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 132 | /* |
| 133 | * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the |
| 134 | * provided platform value |
| 135 | */ |
| 136 | val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; |
| 137 | /* |
| 138 | * If CWG is zero, then no CWG information is available but we can |
| 139 | * at least check the platform value is less than the architectural |
| 140 | * maximum. |
| 141 | */ |
| 142 | if (val != 0) |
| 143 | assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); |
| 144 | else |
| 145 | assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); |
| 146 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 147 | |
| 148 | /* Perform remaining generic architectural setup from EL3 */ |
| 149 | bl1_arch_setup(); |
| 150 | |
| 151 | /* Perform platform setup in BL1. */ |
| 152 | bl1_platform_setup(); |
| 153 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 154 | SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); |
| 155 | SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0); |
| 156 | |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 157 | /* Find out how much free trusted ram remains after BL1 load */ |
Sandrine Bailleux | ee12f6f | 2013-11-28 14:55:58 +0000 | [diff] [blame] | 158 | bl1_tzram_layout = bl1_plat_sec_mem_layout(); |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 159 | |
Juan Castillo | 3a66aca | 2015-04-13 17:36:19 +0100 | [diff] [blame] | 160 | INFO("BL1: Loading BL2\n"); |
| 161 | |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 162 | #if TRUSTED_BOARD_BOOT |
| 163 | /* Initialize authentication module */ |
Juan Castillo | a08a5e7 | 2015-05-19 11:54:12 +0100 | [diff] [blame] | 164 | auth_mod_init(); |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 165 | #endif /* TRUSTED_BOARD_BOOT */ |
| 166 | |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 167 | /* Load the BL2 image */ |
Juan Castillo | a08a5e7 | 2015-05-19 11:54:12 +0100 | [diff] [blame] | 168 | err = load_auth_image(bl1_tzram_layout, |
Juan Castillo | 3a66aca | 2015-04-13 17:36:19 +0100 | [diff] [blame] | 169 | BL2_IMAGE_ID, |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 170 | BL2_BASE, |
| 171 | &bl2_image_info, |
| 172 | &bl2_ep); |
Juan Castillo | a08a5e7 | 2015-05-19 11:54:12 +0100 | [diff] [blame] | 173 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 174 | if (err) { |
| 175 | /* |
| 176 | * TODO: print failure to load BL2 but also add a tzwdog timer |
| 177 | * which will reset the system eventually. |
| 178 | */ |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 179 | ERROR("Failed to load BL2 firmware.\n"); |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 180 | panic(); |
| 181 | } |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 182 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 183 | /* |
| 184 | * Create a new layout of memory for BL2 as seen by BL1 i.e. |
| 185 | * tell it the amount of total and free memory available. |
| 186 | * This layout is created at the first free address visible |
| 187 | * to BL2. BL2 will read the memory layout before using its |
| 188 | * memory for other purposes. |
| 189 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 190 | bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; |
Sandrine Bailleux | 467d057 | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 191 | bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 192 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 193 | bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep); |
| 194 | bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout; |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 195 | NOTICE("BL1: Booting BL2\n"); |
| 196 | INFO("BL1: BL2 address = 0x%llx\n", |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 197 | (unsigned long long) bl2_ep.pc); |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 198 | INFO("BL1: BL2 spsr = 0x%x\n", bl2_ep.spsr); |
| 199 | VERBOSE("BL1: BL2 memory layout address = 0x%llx\n", |
| 200 | (unsigned long long) bl2_tzram_layout); |
| 201 | |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 202 | bl1_run_bl2(&bl2_ep); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 203 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 204 | return; |
| 205 | } |
| 206 | |
| 207 | /******************************************************************************* |
| 208 | * Temporary function to print the fact that BL2 has done its job and BL31 is |
| 209 | * about to be loaded. This is needed as long as printfs cannot be used |
| 210 | ******************************************************************************/ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 211 | void display_boot_progress(entry_point_info_t *bl31_ep_info) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 212 | { |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 213 | NOTICE("BL1: Booting BL3-1\n"); |
| 214 | INFO("BL1: BL3-1 address = 0x%llx\n", |
| 215 | (unsigned long long)bl31_ep_info->pc); |
| 216 | INFO("BL1: BL3-1 spsr = 0x%llx\n", |
| 217 | (unsigned long long)bl31_ep_info->spsr); |
| 218 | INFO("BL1: BL3-1 params address = 0x%llx\n", |
| 219 | (unsigned long long)bl31_ep_info->args.arg0); |
| 220 | INFO("BL1: BL3-1 plat params address = 0x%llx\n", |
| 221 | (unsigned long long)bl31_ep_info->args.arg1); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 222 | } |