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Roberto Vargase0e99462017-10-30 14:43:43 +00001/*
Jiafei Pan0824b452022-02-24 10:47:33 +08002 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
Roberto Vargase0e99462017-10-30 14:43:43 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Masahiro Yamada0b67e562020-03-09 17:39:48 +09007#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <lib/xlat_tables/xlat_tables_defs.h>
Roberto Vargase0e99462017-10-30 14:43:43 +00009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
Jiafei Pan43a7bf42018-03-21 07:20:09 +000015#if BL2_IN_XIP_MEM
16 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
17 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
18#else
Roberto Vargase0e99462017-10-30 14:43:43 +000019 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
Yann Gautier4f5d81d2022-03-31 14:42:11 +020020#endif
Jiafei Pan0824b452022-02-24 10:47:33 +080021#if SEPARATE_BL2_NOLOAD_REGION
22 RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START
23#else
24#define RAM_NOLOAD RAM
25#endif
Roberto Vargase0e99462017-10-30 14:43:43 +000026}
27
Masahiro Yamada5289b672019-06-14 17:49:17 +090028#if !BL2_IN_XIP_MEM
29#define ROM RAM
30#endif
Roberto Vargase0e99462017-10-30 14:43:43 +000031
32SECTIONS
33{
Jiafei Pan43a7bf42018-03-21 07:20:09 +000034#if BL2_IN_XIP_MEM
35 . = BL2_RO_BASE;
36 ASSERT(. == ALIGN(PAGE_SIZE),
37 "BL2_RO_BASE address is not aligned on a page boundary.")
38#else
Roberto Vargase0e99462017-10-30 14:43:43 +000039 . = BL2_BASE;
40 ASSERT(. == ALIGN(PAGE_SIZE),
41 "BL2_BASE address is not aligned on a page boundary.")
Jiafei Pan43a7bf42018-03-21 07:20:09 +000042#endif
Roberto Vargase0e99462017-10-30 14:43:43 +000043
44#if SEPARATE_CODE_AND_RODATA
45 .text . : {
46 __TEXT_START__ = .;
Roberto Vargas51abc342017-11-17 10:51:54 +000047 __TEXT_RESIDENT_START__ = .;
48 *bl2_el3_entrypoint.o(.text*)
49 *(.text.asm.*)
50 __TEXT_RESIDENT_END__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050051 *(SORT_BY_ALIGNMENT(.text*))
Roberto Vargase0e99462017-10-30 14:43:43 +000052 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010053 . = ALIGN(PAGE_SIZE);
Roberto Vargase0e99462017-10-30 14:43:43 +000054 __TEXT_END__ = .;
Jiafei Pan43a7bf42018-03-21 07:20:09 +000055 } >ROM
Roberto Vargase0e99462017-10-30 14:43:43 +000056
57 .rodata . : {
58 __RODATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050059 *(SORT_BY_ALIGNMENT(.rodata*))
Roberto Vargase0e99462017-10-30 14:43:43 +000060
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090061 RODATA_COMMON
Masahiro Yamada65d699d2020-01-17 13:45:02 +090062
Roberto Vargasd93fde32018-04-11 11:53:31 +010063 . = ALIGN(PAGE_SIZE);
Roberto Vargase0e99462017-10-30 14:43:43 +000064 __RODATA_END__ = .;
Jiafei Pan43a7bf42018-03-21 07:20:09 +000065 } >ROM
Roberto Vargas51abc342017-11-17 10:51:54 +000066
67 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
68 "Resident part of BL2 has exceeded its limit.")
Roberto Vargase0e99462017-10-30 14:43:43 +000069#else
70 ro . : {
71 __RO_START__ = .;
Roberto Vargas51abc342017-11-17 10:51:54 +000072 __TEXT_RESIDENT_START__ = .;
73 *bl2_el3_entrypoint.o(.text*)
74 *(.text.asm.*)
75 __TEXT_RESIDENT_END__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050076 *(SORT_BY_ALIGNMENT(.text*))
77 *(SORT_BY_ALIGNMENT(.rodata*))
Roberto Vargase0e99462017-10-30 14:43:43 +000078
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090079 RODATA_COMMON
Masahiro Yamada65d699d2020-01-17 13:45:02 +090080
Roberto Vargase0e99462017-10-30 14:43:43 +000081 *(.vectors)
82 __RO_END_UNALIGNED__ = .;
83 /*
84 * Memory page(s) mapped to this section will be marked as
85 * read-only, executable. No RW data from the next section must
86 * creep in. Ensure the rest of the current memory page is unused.
87 */
Roberto Vargasd93fde32018-04-11 11:53:31 +010088 . = ALIGN(PAGE_SIZE);
Roberto Vargase0e99462017-10-30 14:43:43 +000089
90 __RO_END__ = .;
Jiafei Pan43a7bf42018-03-21 07:20:09 +000091 } >ROM
Jiafei Pan43a7bf42018-03-21 07:20:09 +000092#endif
Roberto Vargase0e99462017-10-30 14:43:43 +000093
94 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
95 "cpu_ops not defined for this platform.")
96
Jiafei Pan43a7bf42018-03-21 07:20:09 +000097#if BL2_IN_XIP_MEM
98 . = BL2_RW_BASE;
99 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
100 "BL2_RW_BASE address is not aligned on a page boundary.")
101#endif
102
Roberto Vargase0e99462017-10-30 14:43:43 +0000103 /*
104 * Define a linker symbol to mark start of the RW memory area for this
105 * image.
106 */
107 __RW_START__ = . ;
108
Masahiro Yamadac5864d82020-04-22 10:50:12 +0900109 DATA_SECTION >RAM AT>ROM
110 __DATA_RAM_START__ = __DATA_START__;
111 __DATA_RAM_END__ = __DATA_END__;
Roberto Vargase0e99462017-10-30 14:43:43 +0000112
Masahiro Yamada85fa00e2020-04-22 11:27:55 +0900113 RELA_SECTION >RAM
Jiafei Pan0824b452022-02-24 10:47:33 +0800114#if SEPARATE_BL2_NOLOAD_REGION
115 SAVED_ADDR = .;
116 . = BL2_NOLOAD_START;
117 __BL2_NOLOAD_START__ = .;
118#endif
119 STACK_SECTION >RAM_NOLOAD
120 BSS_SECTION >RAM_NOLOAD
121 XLAT_TABLE_SECTION >RAM_NOLOAD
122#if SEPARATE_BL2_NOLOAD_REGION
123 __BL2_NOLOAD_END__ = .;
124 . = SAVED_ADDR;
125#endif
Roberto Vargase0e99462017-10-30 14:43:43 +0000126
127#if USE_COHERENT_MEM
128 /*
129 * The base address of the coherent memory section must be page-aligned (4K)
130 * to guarantee that the coherent data are stored on their own pages and
131 * are not mixed with normal data. This is required to set up the correct
132 * memory attributes for the coherent data page tables.
133 */
134 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
135 __COHERENT_RAM_START__ = .;
136 *(tzfw_coherent_mem)
137 __COHERENT_RAM_END_UNALIGNED__ = .;
138 /*
139 * Memory page(s) mapped to this section will be marked
140 * as device memory. No other unexpected data must creep in.
141 * Ensure the rest of the current memory page is unused.
142 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100143 . = ALIGN(PAGE_SIZE);
Roberto Vargase0e99462017-10-30 14:43:43 +0000144 __COHERENT_RAM_END__ = .;
145 } >RAM
146#endif
147
148 /*
149 * Define a linker symbol to mark end of the RW memory area for this
150 * image.
151 */
152 __RW_END__ = .;
153 __BL2_END__ = .;
154
Masahiro Yamada65d699d2020-01-17 13:45:02 +0900155 /DISCARD/ : {
156 *(.dynsym .dynstr .hash .gnu.hash)
157 }
158
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000159#if BL2_IN_XIP_MEM
160 __BL2_RAM_START__ = ADDR(.data);
161 __BL2_RAM_END__ = .;
162
163 __DATA_ROM_START__ = LOADADDR(.data);
164 __DATA_SIZE__ = SIZEOF(.data);
165
166 /*
167 * The .data section is the last PROGBITS section so its end marks the end
168 * of BL2's RO content in XIP memory..
169 */
170 __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
171 ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
172 "BL2's RO content has exceeded its limit.")
173#endif
Roberto Vargase0e99462017-10-30 14:43:43 +0000174 __BSS_SIZE__ = SIZEOF(.bss);
175
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000176
Roberto Vargase0e99462017-10-30 14:43:43 +0000177#if USE_COHERENT_MEM
178 __COHERENT_RAM_UNALIGNED_SIZE__ =
179 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
180#endif
181
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000182#if BL2_IN_XIP_MEM
183 ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
184#else
Roberto Vargase0e99462017-10-30 14:43:43 +0000185 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000186#endif
Roberto Vargase0e99462017-10-30 14:43:43 +0000187}