David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 1 | /* |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 9 | #include <cortex_a75.h> |
Dimitris Papastamos | 1be747f | 2018-02-14 10:28:36 +0000 | [diff] [blame] | 10 | #include <cpuamu.h> |
| 11 | #include <cpu_macros.S> |
Dimitris Papastamos | d7e2e9e | 2017-12-11 11:45:35 +0000 | [diff] [blame] | 12 | |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 13 | /* -------------------------------------------------- |
| 14 | * Errata Workaround for Cortex A75 Errata #764081. |
| 15 | * This applies only to revision r0p0 of Cortex A75. |
| 16 | * Inputs: |
| 17 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 18 | * Shall clobber: x0-x17 |
| 19 | * -------------------------------------------------- |
| 20 | */ |
| 21 | func errata_a75_764081_wa |
| 22 | /* |
| 23 | * Compare x0 against revision r0p0 |
| 24 | */ |
| 25 | mov x17, x30 |
| 26 | bl check_errata_764081 |
| 27 | cbz x0, 1f |
| 28 | mrs x1, sctlr_el3 |
| 29 | orr x1, x1 ,#SCTLR_IESB_BIT |
| 30 | msr sctlr_el3, x1 |
| 31 | isb |
| 32 | 1: |
| 33 | ret x17 |
| 34 | endfunc errata_a75_764081_wa |
| 35 | |
| 36 | func check_errata_764081 |
| 37 | mov x1, #0x00 |
| 38 | b cpu_rev_var_ls |
| 39 | endfunc check_errata_764081 |
| 40 | |
Louis Mayencourt | 8d86870 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 41 | /* -------------------------------------------------- |
| 42 | * Errata Workaround for Cortex A75 Errata #790748. |
| 43 | * This applies only to revision r0p0 of Cortex A75. |
| 44 | * Inputs: |
| 45 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 46 | * Shall clobber: x0-x17 |
| 47 | * -------------------------------------------------- |
| 48 | */ |
| 49 | func errata_a75_790748_wa |
| 50 | /* |
| 51 | * Compare x0 against revision r0p0 |
| 52 | */ |
| 53 | mov x17, x30 |
| 54 | bl check_errata_790748 |
| 55 | cbz x0, 1f |
| 56 | mrs x1, CORTEX_A75_CPUACTLR_EL1 |
| 57 | orr x1, x1 ,#(1 << 13) |
| 58 | msr CORTEX_A75_CPUACTLR_EL1, x1 |
| 59 | isb |
| 60 | 1: |
| 61 | ret x17 |
| 62 | endfunc errata_a75_790748_wa |
| 63 | |
| 64 | func check_errata_790748 |
| 65 | mov x1, #0x00 |
| 66 | b cpu_rev_var_ls |
| 67 | endfunc check_errata_790748 |
| 68 | |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 69 | /* ------------------------------------------------- |
| 70 | * The CPU Ops reset function for Cortex-A75. |
| 71 | * ------------------------------------------------- |
| 72 | */ |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 73 | func cortex_a75_reset_func |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 74 | mov x19, x30 |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 75 | bl cpu_get_rev_var |
Louis Mayencourt | 8d86870 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 76 | mov x18, x0 |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 77 | |
| 78 | #if ERRATA_A75_764081 |
Louis Mayencourt | 8d86870 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 79 | mov x0, x18 |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 80 | bl errata_a75_764081_wa |
| 81 | #endif |
| 82 | |
Louis Mayencourt | 8d86870 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 83 | #if ERRATA_A75_790748 |
| 84 | mov x0, x18 |
| 85 | bl errata_a75_790748_wa |
| 86 | #endif |
| 87 | |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 88 | #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 89 | cpu_check_csv2 x0, 1f |
Dimitris Papastamos | 570c06a | 2018-04-06 15:29:34 +0100 | [diff] [blame] | 90 | adr x0, wa_cve_2017_5715_bpiall_vbar |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 91 | msr vbar_el3, x0 |
Dimitris Papastamos | bb0aa39 | 2018-06-07 13:20:19 +0100 | [diff] [blame] | 92 | isb |
Dimitris Papastamos | 43e05ec | 2018-01-02 15:53:01 +0000 | [diff] [blame] | 93 | 1: |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 94 | #endif |
| 95 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 96 | #if WORKAROUND_CVE_2018_3639 |
| 97 | mrs x0, CORTEX_A75_CPUACTLR_EL1 |
| 98 | orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE |
| 99 | msr CORTEX_A75_CPUACTLR_EL1, x0 |
| 100 | isb |
| 101 | #endif |
| 102 | |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 103 | #if ERRATA_DSU_936184 |
| 104 | bl errata_dsu_936184_wa |
| 105 | #endif |
| 106 | |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 107 | #if ENABLE_AMU |
| 108 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 109 | mrs x0, actlr_el3 |
| 110 | orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT |
| 111 | msr actlr_el3, x0 |
| 112 | isb |
| 113 | |
| 114 | /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
| 115 | mrs x0, actlr_el2 |
| 116 | orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT |
| 117 | msr actlr_el2, x0 |
| 118 | isb |
| 119 | |
| 120 | /* Enable group0 counters */ |
| 121 | mov x0, #CORTEX_A75_AMU_GROUP0_MASK |
| 122 | msr CPUAMCNTENSET_EL0, x0 |
| 123 | isb |
| 124 | |
| 125 | /* Enable group1 counters */ |
| 126 | mov x0, #CORTEX_A75_AMU_GROUP1_MASK |
| 127 | msr CPUAMCNTENSET_EL0, x0 |
| 128 | isb |
| 129 | #endif |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 130 | ret x19 |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 131 | endfunc cortex_a75_reset_func |
| 132 | |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 133 | func check_errata_cve_2017_5715 |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 134 | cpu_check_csv2 x0, 1f |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 135 | #if WORKAROUND_CVE_2017_5715 |
| 136 | mov x0, #ERRATA_APPLIES |
| 137 | #else |
| 138 | mov x0, #ERRATA_MISSING |
| 139 | #endif |
| 140 | ret |
| 141 | 1: |
| 142 | mov x0, #ERRATA_NOT_APPLIES |
| 143 | ret |
| 144 | endfunc check_errata_cve_2017_5715 |
| 145 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 146 | func check_errata_cve_2018_3639 |
| 147 | #if WORKAROUND_CVE_2018_3639 |
| 148 | mov x0, #ERRATA_APPLIES |
| 149 | #else |
| 150 | mov x0, #ERRATA_MISSING |
| 151 | #endif |
| 152 | ret |
| 153 | endfunc check_errata_cve_2018_3639 |
| 154 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 155 | /* --------------------------------------------- |
| 156 | * HW will do the cache maintenance while powering down |
| 157 | * --------------------------------------------- |
| 158 | */ |
| 159 | func cortex_a75_core_pwr_dwn |
| 160 | /* --------------------------------------------- |
| 161 | * Enable CPU power down bit in power control register |
| 162 | * --------------------------------------------- |
| 163 | */ |
| 164 | mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 |
| 165 | orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK |
| 166 | msr CORTEX_A75_CPUPWRCTLR_EL1, x0 |
| 167 | isb |
| 168 | ret |
| 169 | endfunc cortex_a75_core_pwr_dwn |
| 170 | |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 171 | #if REPORT_ERRATA |
| 172 | /* |
| 173 | * Errata printing function for Cortex A75. Must follow AAPCS. |
| 174 | */ |
| 175 | func cortex_a75_errata_report |
| 176 | stp x8, x30, [sp, #-16]! |
| 177 | |
| 178 | bl cpu_get_rev_var |
| 179 | mov x8, x0 |
| 180 | |
| 181 | /* |
| 182 | * Report all errata. The revision-variant information is passed to |
| 183 | * checking functions of each errata. |
| 184 | */ |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 185 | report_errata ERRATA_A75_764081, cortex_a75, 764081 |
Louis Mayencourt | 8d86870 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 186 | report_errata ERRATA_A75_790748, cortex_a75, 790748 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 187 | report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 188 | report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 189 | report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 190 | |
| 191 | ldp x8, x30, [sp], #16 |
| 192 | ret |
| 193 | endfunc cortex_a75_errata_report |
| 194 | #endif |
| 195 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 196 | /* --------------------------------------------- |
| 197 | * This function provides cortex_a75 specific |
| 198 | * register information for crash reporting. |
| 199 | * It needs to return with x6 pointing to |
| 200 | * a list of register names in ascii and |
| 201 | * x8 - x15 having values of registers to be |
| 202 | * reported. |
| 203 | * --------------------------------------------- |
| 204 | */ |
| 205 | .section .rodata.cortex_a75_regs, "aS" |
| 206 | cortex_a75_regs: /* The ascii list of register names to be reported */ |
| 207 | .asciz "cpuectlr_el1", "" |
| 208 | |
| 209 | func cortex_a75_cpu_reg_dump |
| 210 | adr x6, cortex_a75_regs |
| 211 | mrs x8, CORTEX_A75_CPUECTLR_EL1 |
| 212 | ret |
| 213 | endfunc cortex_a75_cpu_reg_dump |
| 214 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 215 | declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 216 | cortex_a75_reset_func, \ |
Dimitris Papastamos | 914757c | 2018-03-12 14:47:09 +0000 | [diff] [blame] | 217 | check_errata_cve_2017_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 218 | CPU_NO_EXTRA2_FUNC, \ |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 219 | cortex_a75_core_pwr_dwn |