Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 32 | #include <assert.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 33 | #include <bakery_lock.h> |
| 34 | #include <css_def.h> |
| 35 | #include <mmio.h> |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 36 | #include <platform_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 37 | #include <plat_arm.h> |
| 38 | #include "css_mhu.h" |
| 39 | |
| 40 | /* SCP MHU secure channel registers */ |
| 41 | #define SCP_INTR_S_STAT 0x200 |
| 42 | #define SCP_INTR_S_SET 0x208 |
| 43 | #define SCP_INTR_S_CLEAR 0x210 |
| 44 | |
| 45 | /* CPU MHU secure channel registers */ |
| 46 | #define CPU_INTR_S_STAT 0x300 |
| 47 | #define CPU_INTR_S_SET 0x308 |
| 48 | #define CPU_INTR_S_CLEAR 0x310 |
| 49 | |
| 50 | ARM_INSTANTIATE_LOCK |
| 51 | |
| 52 | /* Weak definition may be overridden in specific CSS based platform */ |
| 53 | #pragma weak plat_arm_pwrc_setup |
| 54 | |
| 55 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 56 | /* |
| 57 | * Slot 31 is reserved because the MHU hardware uses this register bit to |
| 58 | * indicate a non-secure access attempt. The total number of available slots is |
| 59 | * therefore 31 [30:0]. |
| 60 | */ |
| 61 | #define MHU_MAX_SLOT_ID 30 |
| 62 | |
| 63 | void mhu_secure_message_start(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 64 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 65 | assert(slot_id <= MHU_MAX_SLOT_ID); |
| 66 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 67 | arm_lock_get(); |
| 68 | |
| 69 | /* Make sure any previous command has finished */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 70 | while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & |
| 71 | (1 << slot_id)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 72 | ; |
| 73 | } |
| 74 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 75 | void mhu_secure_message_send(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 76 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 77 | assert(slot_id <= MHU_MAX_SLOT_ID); |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 78 | assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & |
| 79 | (1 << slot_id))); |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 80 | |
| 81 | /* Send command to SCP */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 82 | mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | uint32_t mhu_secure_message_wait(void) |
| 86 | { |
| 87 | /* Wait for response from SCP */ |
| 88 | uint32_t response; |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 89 | while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT))) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 90 | ; |
| 91 | |
| 92 | return response; |
| 93 | } |
| 94 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 95 | void mhu_secure_message_end(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 96 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 97 | assert(slot_id <= MHU_MAX_SLOT_ID); |
| 98 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 99 | /* |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 100 | * Clear any response we got by writing one in the relevant slot bit to |
| 101 | * the CLEAR register |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 102 | */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 103 | mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 104 | |
| 105 | arm_lock_release(); |
| 106 | } |
| 107 | |
| 108 | void mhu_secure_init(void) |
| 109 | { |
| 110 | arm_lock_init(); |
| 111 | |
| 112 | /* |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 113 | * The STAT register resets to zero. Ensure it is in the expected state, |
| 114 | * as a stale or garbage value would make us think it's a message we've |
| 115 | * already sent. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 116 | */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 117 | assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | void plat_arm_pwrc_setup(void) |
| 121 | { |
| 122 | mhu_secure_init(); |
| 123 | } |