blob: 2a75790093fe5c9267696cf770e150b57ebf435b [file] [log] [blame]
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8#include <arch_helpers.h>
9#include <assert.h>
10#include <psci.h>
11#include <marvell_pm.h>
12
13/* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */
14extern const plat_psci_ops_t plat_arm_psci_pm_ops;
15
16/*****************************************************************************
17 * Private function to program the mailbox for a cpu before it is released
18 * from reset. This function assumes that the mail box base is within
19 * the MARVELL_SHARED_RAM region
20 *****************************************************************************
21 */
22void marvell_program_mailbox(uintptr_t address)
23{
24 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
25
26 /*
27 * Ensure that the PLAT_MARVELL_MAILBOX_BASE is within
28 * MARVELL_SHARED_RAM region.
29 */
30 assert((PLAT_MARVELL_MAILBOX_BASE >= MARVELL_SHARED_RAM_BASE) &&
31 ((PLAT_MARVELL_MAILBOX_BASE + sizeof(*mailbox)) <=
32 (MARVELL_SHARED_RAM_BASE + MARVELL_SHARED_RAM_SIZE)));
33
34 mailbox[MBOX_IDX_MAGIC] = MVEBU_MAILBOX_MAGIC_NUM;
35 mailbox[MBOX_IDX_SEC_ADDR] = address;
36
37 /* Flush data cache if the mail box shared RAM is cached */
38#if PLAT_MARVELL_SHARED_RAM_CACHED
39 flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE +
40 8 * MBOX_IDX_MAGIC,
41 2 * sizeof(uint64_t));
42#endif
43}
44
45/*****************************************************************************
46 * The ARM Standard platform definition of platform porting API
47 * `plat_setup_psci_ops`.
48 *****************************************************************************
49 */
50int plat_setup_psci_ops(uintptr_t sec_entrypoint,
51 const plat_psci_ops_t **psci_ops)
52{
53 *psci_ops = &plat_arm_psci_pm_ops;
54
55 /* Setup mailbox with entry point. */
56 marvell_program_mailbox(sec_entrypoint);
57 return 0;
58}