Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
| 8 | #include <debug.h> |
| 9 | #include <mmio.h> |
| 10 | #include "qos_init.h" |
| 11 | #include "qos_common.h" |
| 12 | #if RCAR_LSI == RCAR_AUTO |
| 13 | #include "H3/qos_init_h3_v10.h" |
| 14 | #include "H3/qos_init_h3_v11.h" |
| 15 | #include "H3/qos_init_h3_v20.h" |
| 16 | #include "H3/qos_init_h3_v30.h" |
| 17 | #include "M3/qos_init_m3_v10.h" |
| 18 | #include "M3/qos_init_m3_v11.h" |
| 19 | #include "M3N/qos_init_m3n_v10.h" |
| 20 | #endif |
| 21 | #if RCAR_LSI == RCAR_H3 /* H3 */ |
| 22 | #include "H3/qos_init_h3_v10.h" |
| 23 | #include "H3/qos_init_h3_v11.h" |
| 24 | #include "H3/qos_init_h3_v20.h" |
| 25 | #include "H3/qos_init_h3_v30.h" |
| 26 | #endif |
| 27 | #if RCAR_LSI == RCAR_H3N /* H3 */ |
| 28 | #include "H3/qos_init_h3n_v30.h" |
| 29 | #endif |
| 30 | #if RCAR_LSI == RCAR_M3 /* M3 */ |
| 31 | #include "M3/qos_init_m3_v10.h" |
| 32 | #include "M3/qos_init_m3_v11.h" |
| 33 | #endif |
| 34 | #if RCAR_LSI == RCAR_M3N /* M3N */ |
| 35 | #include "M3N/qos_init_m3n_v10.h" |
| 36 | #endif |
| 37 | #if RCAR_LSI == RCAR_E3 /* E3 */ |
| 38 | #include "E3/qos_init_e3_v10.h" |
| 39 | #endif |
| 40 | |
| 41 | /* Product Register */ |
| 42 | #define PRR (0xFFF00044U) |
| 43 | #define PRR_PRODUCT_MASK (0x00007F00U) |
| 44 | #define PRR_CUT_MASK (0x000000FFU) |
| 45 | #define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ |
| 46 | #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ |
| 47 | #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ |
| 48 | #define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ |
| 49 | #define PRR_PRODUCT_10 (0x00U) |
| 50 | #define PRR_PRODUCT_11 (0x01U) |
| 51 | #define PRR_PRODUCT_20 (0x10U) |
| 52 | #define PRR_PRODUCT_30 (0x20U) |
| 53 | |
| 54 | #if !(RCAR_LSI == RCAR_E3) |
| 55 | |
| 56 | #define DRAM_CH_CNT 0x04 |
| 57 | uint32_t qos_init_ddr_ch; |
| 58 | uint8_t qos_init_ddr_phyvalid; |
| 59 | |
| 60 | #endif |
| 61 | |
| 62 | #define PRR_PRODUCT_ERR(reg) \ |
| 63 | do{ \ |
| 64 | ERROR("LSI Product ID(PRR=0x%x) QoS " \ |
| 65 | "initialize not supported.\n",reg); \ |
| 66 | panic(); \ |
| 67 | } while(0) |
| 68 | |
| 69 | #define PRR_CUT_ERR(reg) \ |
| 70 | do{ \ |
| 71 | ERROR("LSI Cut ID(PRR=0x%x) QoS " \ |
| 72 | "initialize not supported.\n",reg); \ |
| 73 | panic(); \ |
| 74 | } while(0) |
| 75 | |
| 76 | void rcar_qos_init(void) |
| 77 | { |
| 78 | uint32_t reg; |
| 79 | #if !(RCAR_LSI == RCAR_E3) |
| 80 | uint32_t i; |
| 81 | |
| 82 | qos_init_ddr_ch = 0; |
| 83 | qos_init_ddr_phyvalid = get_boardcnf_phyvalid(); |
| 84 | for (i = 0; i < DRAM_CH_CNT; i++) { |
| 85 | if ((qos_init_ddr_phyvalid & (1 << i))) { |
| 86 | qos_init_ddr_ch++; |
| 87 | } |
| 88 | } |
| 89 | #endif |
| 90 | |
| 91 | reg = mmio_read_32(PRR); |
| 92 | #if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT |
| 93 | switch (reg & PRR_PRODUCT_MASK) { |
| 94 | case PRR_PRODUCT_H3: |
| 95 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) |
| 96 | switch (reg & PRR_CUT_MASK) { |
| 97 | case PRR_PRODUCT_10: |
| 98 | qos_init_h3_v10(); |
| 99 | break; |
| 100 | case PRR_PRODUCT_11: |
| 101 | qos_init_h3_v11(); |
| 102 | break; |
| 103 | case PRR_PRODUCT_20: |
| 104 | qos_init_h3_v20(); |
| 105 | break; |
| 106 | case PRR_PRODUCT_30: |
| 107 | default: |
| 108 | qos_init_h3_v30(); |
| 109 | break; |
| 110 | } |
| 111 | #elif (RCAR_LSI == RCAR_H3N) |
| 112 | switch (reg & PRR_CUT_MASK) { |
| 113 | case PRR_PRODUCT_30: |
| 114 | default: |
| 115 | qos_init_h3n_v30(); |
| 116 | break; |
| 117 | } |
| 118 | #else |
| 119 | PRR_PRODUCT_ERR(reg); |
| 120 | #endif |
| 121 | break; |
| 122 | case PRR_PRODUCT_M3: |
| 123 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) |
| 124 | switch (reg & PRR_CUT_MASK) { |
| 125 | case PRR_PRODUCT_10: |
| 126 | qos_init_m3_v10(); |
| 127 | break; |
| 128 | case PRR_PRODUCT_20: /* M3 Cut 11 */ |
| 129 | default: |
| 130 | qos_init_m3_v11(); |
| 131 | break; |
| 132 | } |
| 133 | #else |
| 134 | PRR_PRODUCT_ERR(reg); |
| 135 | #endif |
| 136 | break; |
| 137 | case PRR_PRODUCT_M3N: |
| 138 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) |
| 139 | switch (reg & PRR_CUT_MASK) { |
| 140 | case PRR_PRODUCT_10: |
| 141 | default: |
| 142 | qos_init_m3n_v10(); |
| 143 | break; |
| 144 | } |
| 145 | #else |
| 146 | PRR_PRODUCT_ERR(reg); |
| 147 | #endif |
| 148 | break; |
| 149 | case PRR_PRODUCT_E3: |
| 150 | #if (RCAR_LSI == RCAR_E3) |
| 151 | switch (reg & PRR_CUT_MASK) { |
| 152 | case PRR_PRODUCT_10: |
| 153 | default: |
| 154 | qos_init_e3_v10(); |
| 155 | break; |
| 156 | } |
| 157 | #else |
| 158 | PRR_PRODUCT_ERR(reg); |
| 159 | #endif |
| 160 | break; |
| 161 | default: |
| 162 | PRR_PRODUCT_ERR(reg); |
| 163 | break; |
| 164 | } |
| 165 | #else |
| 166 | #if RCAR_LSI == RCAR_H3 /* H3 */ |
| 167 | #if RCAR_LSI_CUT == RCAR_CUT_10 |
| 168 | /* H3 Cut 10 */ |
| 169 | if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10) |
| 170 | != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { |
| 171 | PRR_PRODUCT_ERR(reg); |
| 172 | } |
| 173 | qos_init_h3_v10(); |
| 174 | #elif RCAR_LSI_CUT == RCAR_CUT_11 |
| 175 | /* H3 Cut 11 */ |
| 176 | if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11) |
| 177 | != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { |
| 178 | PRR_PRODUCT_ERR(reg); |
| 179 | } |
| 180 | qos_init_h3_v11(); |
| 181 | #elif RCAR_LSI_CUT == RCAR_CUT_20 |
| 182 | /* H3 Cut 20 */ |
| 183 | if ((PRR_PRODUCT_H3 | PRR_PRODUCT_20) |
| 184 | != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { |
| 185 | PRR_PRODUCT_ERR(reg); |
| 186 | } |
| 187 | qos_init_h3_v20(); |
| 188 | #else |
| 189 | /* H3 Cut 30 or later */ |
| 190 | if ((PRR_PRODUCT_H3) |
| 191 | != (reg & (PRR_PRODUCT_MASK))) { |
| 192 | PRR_PRODUCT_ERR(reg); |
| 193 | } |
| 194 | qos_init_h3_v30(); |
| 195 | #endif |
| 196 | #elif RCAR_LSI == RCAR_H3N /* H3 */ |
| 197 | /* H3N Cut 30 or later */ |
| 198 | if ((PRR_PRODUCT_H3) |
| 199 | != (reg & (PRR_PRODUCT_MASK))) { |
| 200 | PRR_PRODUCT_ERR(reg); |
| 201 | } |
| 202 | qos_init_h3n_v30(); |
| 203 | #elif RCAR_LSI == RCAR_M3 /* M3 */ |
| 204 | #if RCAR_LSI_CUT == RCAR_CUT_10 |
| 205 | /* M3 Cut 10 */ |
| 206 | if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10) |
| 207 | != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { |
| 208 | PRR_PRODUCT_ERR(reg); |
| 209 | } |
| 210 | qos_init_m3_v10(); |
| 211 | #else |
| 212 | /* M3 Cut 11 or later */ |
| 213 | if ((PRR_PRODUCT_M3) |
| 214 | != (reg & (PRR_PRODUCT_MASK))) { |
| 215 | PRR_PRODUCT_ERR(reg); |
| 216 | } |
| 217 | qos_init_m3_v11(); |
| 218 | #endif |
| 219 | #elif RCAR_LSI == RCAR_M3N /* M3N */ |
| 220 | /* M3N Cut 10 or later */ |
| 221 | if ((PRR_PRODUCT_M3N) |
| 222 | != (reg & (PRR_PRODUCT_MASK))) { |
| 223 | PRR_PRODUCT_ERR(reg); |
| 224 | } |
| 225 | qos_init_m3n_v10(); |
| 226 | #elif RCAR_LSI == RCAR_E3 /* E3 */ |
| 227 | /* E3 Cut 10 or later */ |
| 228 | if ((PRR_PRODUCT_E3) |
| 229 | != (reg & (PRR_PRODUCT_MASK))) { |
| 230 | PRR_PRODUCT_ERR(reg); |
| 231 | } |
| 232 | qos_init_e3_v10(); |
| 233 | #else |
| 234 | #error "Don't have QoS initialize routine(Unknown chip)." |
| 235 | #endif |
| 236 | #endif |
| 237 | } |
| 238 | |
| 239 | uint32_t get_refperiod(void) |
| 240 | { |
| 241 | uint32_t refperiod = QOSWT_WTSET0_CYCLE; |
| 242 | |
| 243 | #if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT |
| 244 | uint32_t reg; |
| 245 | |
| 246 | reg = mmio_read_32(PRR); |
| 247 | switch (reg & PRR_PRODUCT_MASK) { |
| 248 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) |
| 249 | case PRR_PRODUCT_H3: |
| 250 | switch (reg & PRR_CUT_MASK) { |
| 251 | case PRR_PRODUCT_10: |
| 252 | case PRR_PRODUCT_11: |
| 253 | break; |
| 254 | case PRR_PRODUCT_20: |
| 255 | refperiod = QOSWT_WTSET0_CYCLE_H3_20; |
| 256 | break; |
| 257 | case PRR_PRODUCT_30: |
| 258 | default: |
| 259 | refperiod = QOSWT_WTSET0_CYCLE_H3_30; |
| 260 | break; |
| 261 | } |
| 262 | break; |
| 263 | #elif (RCAR_LSI == RCAR_H3N) |
| 264 | case PRR_PRODUCT_H3: |
| 265 | switch (reg & PRR_CUT_MASK) { |
| 266 | case PRR_PRODUCT_30: |
| 267 | default: |
| 268 | refperiod = QOSWT_WTSET0_CYCLE_H3N; |
| 269 | break; |
| 270 | } |
| 271 | break; |
| 272 | #endif |
| 273 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) |
| 274 | case PRR_PRODUCT_M3: |
| 275 | switch (reg & PRR_CUT_MASK) { |
| 276 | case PRR_PRODUCT_10: |
| 277 | break; |
| 278 | case PRR_PRODUCT_20: /* M3 Cut 11 */ |
| 279 | default: |
| 280 | refperiod = QOSWT_WTSET0_CYCLE_M3_11; |
| 281 | break; |
| 282 | } |
| 283 | break; |
| 284 | #endif |
| 285 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) |
| 286 | case PRR_PRODUCT_M3N: |
| 287 | refperiod = QOSWT_WTSET0_CYCLE_M3N; |
| 288 | break; |
| 289 | #endif |
| 290 | #if (RCAR_LSI == RCAR_E3) |
| 291 | case PRR_PRODUCT_E3: |
| 292 | refperiod = QOSWT_WTSET0_CYCLE_E3; |
| 293 | break; |
| 294 | #endif |
| 295 | default: |
| 296 | break; |
| 297 | } |
| 298 | #elif RCAR_LSI == RCAR_H3 |
| 299 | #if RCAR_LSI_CUT == RCAR_CUT_10 |
| 300 | /* H3 Cut 10 */ |
| 301 | #elif RCAR_LSI_CUT == RCAR_CUT_11 |
| 302 | /* H3 Cut 11 */ |
| 303 | #elif RCAR_LSI_CUT == RCAR_CUT_20 |
| 304 | /* H3 Cut 20 */ |
| 305 | refperiod = QOSWT_WTSET0_CYCLE_H3_20; |
| 306 | #else |
| 307 | /* H3 Cut 30 or later */ |
| 308 | refperiod = QOSWT_WTSET0_CYCLE_H3_30; |
| 309 | #endif |
| 310 | #elif RCAR_LSI == RCAR_H3N |
| 311 | /* H3N Cut 30 or later */ |
| 312 | refperiod = QOSWT_WTSET0_CYCLE_H3N; |
| 313 | #elif RCAR_LSI == RCAR_M3 |
| 314 | #if RCAR_LSI_CUT == RCAR_CUT_10 |
| 315 | /* M3 Cut 10 */ |
| 316 | #else |
| 317 | /* M3 Cut 11 or later */ |
| 318 | refperiod = QOSWT_WTSET0_CYCLE_M3_11; |
| 319 | #endif |
| 320 | #elif RCAR_LSI == RCAR_M3N /* for M3N */ |
| 321 | refperiod = QOSWT_WTSET0_CYCLE_M3N; |
| 322 | #elif RCAR_LSI == RCAR_E3 /* for E3 */ |
| 323 | refperiod = QOSWT_WTSET0_CYCLE_E3; |
| 324 | #endif |
| 325 | |
| 326 | return refperiod; |
| 327 | } |