Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 1 | /* |
Tamas Ban | c5d525d | 2023-05-08 13:46:26 +0200 | [diff] [blame] | 2 | * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <plat/common/platform.h> |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <drivers/arm/ccn.h> |
Tamas Ban | c5d525d | 2023-05-08 13:46:26 +0200 | [diff] [blame] | 15 | #include <drivers/arm/css/sds.h> |
| 16 | #include <lib/utils_def.h> |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 17 | #include <plat/arm/common/plat_arm.h> |
| 18 | #include <plat/common/platform.h> |
| 19 | #include <drivers/arm/sbsa.h> |
Olivier Deprez | 21cf360 | 2020-07-30 17:18:33 +0200 | [diff] [blame] | 20 | |
| 21 | #if SPM_MM |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 22 | #include <services/spm_mm_partition.h> |
Olivier Deprez | 21cf360 | 2020-07-30 17:18:33 +0200 | [diff] [blame] | 23 | #endif |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * Table of regions for different BL stages to map using the MMU. |
| 27 | * This doesn't include Trusted RAM as the 'mem_layout' argument passed to |
| 28 | * arm_configure_mmu_elx() will give the available subset of that. |
| 29 | */ |
| 30 | #if IMAGE_BL1 |
| 31 | const mmap_region_t plat_arm_mmap[] = { |
| 32 | ARM_MAP_SHARED_RAM, |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 33 | TC_FLASH0_RO, |
| 34 | TC_MAP_DEVICE, |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 35 | {0} |
| 36 | }; |
| 37 | #endif |
| 38 | #if IMAGE_BL2 |
| 39 | const mmap_region_t plat_arm_mmap[] = { |
| 40 | ARM_MAP_SHARED_RAM, |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 41 | TC_FLASH0_RO, |
| 42 | TC_MAP_DEVICE, |
| 43 | TC_MAP_NS_DRAM1, |
Arunachalam Ganapathy | ade4a20 | 2020-09-22 12:50:45 +0100 | [diff] [blame] | 44 | #if defined(SPD_spmd) |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 45 | TC_MAP_TZC_DRAM1, |
Arunachalam Ganapathy | ade4a20 | 2020-09-22 12:50:45 +0100 | [diff] [blame] | 46 | #endif |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 47 | #if ARM_BL31_IN_DRAM |
| 48 | ARM_MAP_BL31_SEC_DRAM, |
| 49 | #endif |
| 50 | #if SPM_MM |
| 51 | ARM_SP_IMAGE_MMAP, |
| 52 | #endif |
Arvind Ram Prakash | 11b9b49 | 2022-11-22 14:41:00 -0600 | [diff] [blame] | 53 | #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 54 | ARM_MAP_BL1_RW, |
| 55 | #endif |
Arunachalam Ganapathy | 29786f7 | 2020-11-17 14:48:59 +0000 | [diff] [blame] | 56 | #ifdef SPD_opteed |
| 57 | ARM_MAP_OPTEE_CORE_MEM, |
| 58 | ARM_OPTEE_PAGEABLE_LOAD_MEM, |
| 59 | #endif |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 60 | {0} |
| 61 | }; |
| 62 | #endif |
| 63 | #if IMAGE_BL31 |
| 64 | const mmap_region_t plat_arm_mmap[] = { |
| 65 | ARM_MAP_SHARED_RAM, |
| 66 | V2M_MAP_IOFPGA, |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 67 | TC_MAP_DEVICE, |
Usama Arif | a49bd49 | 2021-08-17 17:57:10 +0100 | [diff] [blame] | 68 | PLAT_DTB_DRAM_NS, |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 69 | #if SPM_MM |
| 70 | ARM_SPM_BUF_EL3_MMAP, |
| 71 | #endif |
| 72 | {0} |
| 73 | }; |
| 74 | |
| 75 | #if SPM_MM && defined(IMAGE_BL31) |
| 76 | const mmap_region_t plat_arm_secure_partition_mmap[] = { |
| 77 | PLAT_ARM_SECURE_MAP_DEVICE, |
| 78 | ARM_SP_IMAGE_MMAP, |
| 79 | ARM_SP_IMAGE_NS_BUF_MMAP, |
| 80 | ARM_SP_CPER_BUF_MMAP, |
| 81 | ARM_SP_IMAGE_RW_MMAP, |
| 82 | ARM_SPM_BUF_EL0_MMAP, |
| 83 | {0} |
| 84 | }; |
| 85 | #endif /* SPM_MM && defined(IMAGE_BL31) */ |
| 86 | #endif |
| 87 | |
| 88 | ARM_CASSERT_MMAP |
| 89 | |
| 90 | #if SPM_MM && defined(IMAGE_BL31) |
| 91 | /* |
| 92 | * Boot information passed to a secure partition during initialisation. Linear |
| 93 | * indices in MP information will be filled at runtime. |
| 94 | */ |
| 95 | static spm_mm_mp_info_t sp_mp_info[] = { |
| 96 | [0] = {0x81000000, 0}, |
| 97 | [1] = {0x81000100, 0}, |
| 98 | [2] = {0x81000200, 0}, |
| 99 | [3] = {0x81000300, 0}, |
| 100 | [4] = {0x81010000, 0}, |
| 101 | [5] = {0x81010100, 0}, |
| 102 | [6] = {0x81010200, 0}, |
| 103 | [7] = {0x81010300, 0}, |
| 104 | }; |
| 105 | |
| 106 | const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { |
| 107 | .h.type = PARAM_SP_IMAGE_BOOT_INFO, |
| 108 | .h.version = VERSION_1, |
| 109 | .h.size = sizeof(spm_mm_boot_info_t), |
| 110 | .h.attr = 0, |
| 111 | .sp_mem_base = ARM_SP_IMAGE_BASE, |
| 112 | .sp_mem_limit = ARM_SP_IMAGE_LIMIT, |
| 113 | .sp_image_base = ARM_SP_IMAGE_BASE, |
| 114 | .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, |
| 115 | .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, |
| 116 | .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, |
| 117 | .sp_shared_buf_base = PLAT_SPM_BUF_BASE, |
| 118 | .sp_image_size = ARM_SP_IMAGE_SIZE, |
| 119 | .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, |
| 120 | .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, |
| 121 | .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, |
| 122 | .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, |
| 123 | .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, |
| 124 | .num_cpus = PLATFORM_CORE_COUNT, |
| 125 | .mp_info = &sp_mp_info[0], |
| 126 | }; |
| 127 | |
| 128 | const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) |
| 129 | { |
| 130 | return plat_arm_secure_partition_mmap; |
| 131 | } |
| 132 | |
| 133 | const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( |
| 134 | void *cookie) |
| 135 | { |
| 136 | return &plat_arm_secure_partition_boot_info; |
| 137 | } |
| 138 | #endif /* SPM_MM && defined(IMAGE_BL31) */ |
| 139 | |
Tamas Ban | ede4f05 | 2022-09-16 16:26:15 +0200 | [diff] [blame] | 140 | #if TRUSTED_BOARD_BOOT || MEASURED_BOOT |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 141 | int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) |
| 142 | { |
| 143 | assert(heap_addr != NULL); |
| 144 | assert(heap_size != NULL); |
| 145 | |
| 146 | return arm_get_mbedtls_heap(heap_addr, heap_size); |
| 147 | } |
| 148 | #endif |
| 149 | |
| 150 | void plat_arm_secure_wdt_start(void) |
| 151 | { |
Madhukar Pappireddy | e108df2 | 2023-03-22 15:40:40 -0500 | [diff] [blame] | 152 | sbsa_wdog_start(SBSA_SECURE_WDOG_CONTROL_BASE, SBSA_SECURE_WDOG_TIMEOUT); |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | void plat_arm_secure_wdt_stop(void) |
| 156 | { |
Madhukar Pappireddy | e108df2 | 2023-03-22 15:40:40 -0500 | [diff] [blame] | 157 | sbsa_wdog_stop(SBSA_SECURE_WDOG_CONTROL_BASE); |
| 158 | } |
| 159 | |
| 160 | void plat_arm_secure_wdt_refresh(void) |
| 161 | { |
| 162 | sbsa_wdog_refresh(SBSA_SECURE_WDOG_REFRESH_BASE); |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 163 | } |
Tamas Ban | c5d525d | 2023-05-08 13:46:26 +0200 | [diff] [blame] | 164 | |
| 165 | static sds_region_desc_t tc_sds_regions[] = { |
| 166 | { .base = PLAT_ARM_SDS_MEM_BASE }, |
| 167 | { .base = PLAT_ARM_RSS_AP_SDS_MEM_BASE }, |
| 168 | }; |
| 169 | |
| 170 | sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count) |
| 171 | { |
| 172 | *region_count = ARRAY_SIZE(tc_sds_regions); |
| 173 | |
| 174 | return tc_sds_regions; |
| 175 | } |