Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 1 | /* |
Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __TZC400_H__ |
| 8 | #define __TZC400_H__ |
| 9 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 10 | #include <tzc_common.h> |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 11 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 12 | #define BUILD_CONFIG_OFF 0x000 |
| 13 | #define GATE_KEEPER_OFF 0x008 |
| 14 | #define SPECULATION_CTRL_OFF 0x00c |
| 15 | #define INT_STATUS 0x010 |
| 16 | #define INT_CLEAR 0x014 |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 17 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 18 | #define FAIL_ADDRESS_LOW_OFF 0x020 |
| 19 | #define FAIL_ADDRESS_HIGH_OFF 0x024 |
| 20 | #define FAIL_CONTROL_OFF 0x028 |
| 21 | #define FAIL_ID 0x02c |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 22 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 23 | /* ID registers not common across different varieties of TZC */ |
| 24 | #define PID5 0xFD4 |
| 25 | #define PID6 0xFD8 |
| 26 | #define PID7 0xFDC |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 27 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 28 | #define BUILD_CONFIG_NF_SHIFT 24 |
| 29 | #define BUILD_CONFIG_NF_MASK 0x3 |
| 30 | #define BUILD_CONFIG_AW_SHIFT 8 |
| 31 | #define BUILD_CONFIG_AW_MASK 0x3f |
| 32 | #define BUILD_CONFIG_NR_SHIFT 0 |
| 33 | #define BUILD_CONFIG_NR_MASK 0x1f |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 34 | |
| 35 | /* |
| 36 | * Number of gate keepers is implementation defined. But we know the max for |
| 37 | * this device is 4. Get implementation details from BUILD_CONFIG. |
| 38 | */ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 39 | #define GATE_KEEPER_OS_SHIFT 16 |
| 40 | #define GATE_KEEPER_OS_MASK 0xf |
| 41 | #define GATE_KEEPER_OR_SHIFT 0 |
| 42 | #define GATE_KEEPER_OR_MASK 0xf |
| 43 | #define GATE_KEEPER_FILTER_MASK 0x1 |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 44 | |
| 45 | /* Speculation is enabled by default. */ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 46 | #define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) |
| 47 | #define SPECULATION_CTRL_READ_DISABLE (1 << 0) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 48 | |
| 49 | /* Max number of filters allowed is 4. */ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 50 | #define INT_STATUS_OVERLAP_SHIFT 16 |
| 51 | #define INT_STATUS_OVERLAP_MASK 0xf |
| 52 | #define INT_STATUS_OVERRUN_SHIFT 8 |
| 53 | #define INT_STATUS_OVERRUN_MASK 0xf |
| 54 | #define INT_STATUS_STATUS_SHIFT 0 |
| 55 | #define INT_STATUS_STATUS_MASK 0xf |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 56 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 57 | #define INT_CLEAR_CLEAR_SHIFT 0 |
| 58 | #define INT_CLEAR_CLEAR_MASK 0xf |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 59 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 60 | #define FAIL_CONTROL_DIR_SHIFT (1 << 24) |
| 61 | #define FAIL_CONTROL_DIR_READ 0x0 |
| 62 | #define FAIL_CONTROL_DIR_WRITE 0x1 |
| 63 | #define FAIL_CONTROL_NS_SHIFT (1 << 21) |
| 64 | #define FAIL_CONTROL_NS_SECURE 0x0 |
| 65 | #define FAIL_CONTROL_NS_NONSECURE 0x1 |
| 66 | #define FAIL_CONTROL_PRIV_SHIFT (1 << 20) |
| 67 | #define FAIL_CONTROL_PRIV_PRIV 0x0 |
| 68 | #define FAIL_CONTROL_PRIV_UNPRIV 0x1 |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. |
| 72 | * Platform should provide the value on initialisation. |
| 73 | */ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 74 | #define FAIL_ID_VNET_SHIFT 24 |
| 75 | #define FAIL_ID_VNET_MASK 0xf |
| 76 | #define FAIL_ID_ID_SHIFT 0 |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 77 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 78 | #define TZC_400_PERIPHERAL_ID 0x460 |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 79 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 80 | /* Filter enable bits in a TZC */ |
| 81 | #define TZC_400_REGION_ATTR_F_EN_MASK 0xf |
| 82 | #define TZC_400_REGION_ATTR_FILTER_BIT(x) ((1 << x) \ |
| 83 | << TZC_REGION_ATTR_F_EN_SHIFT) |
| 84 | #define TZC_400_REGION_ATTR_FILTER_BIT_ALL \ |
| 85 | (TZC_400_REGION_ATTR_F_EN_MASK << \ |
| 86 | TZC_REGION_ATTR_F_EN_SHIFT) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 87 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 88 | /* |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 89 | * All TZC region configuration registers are placed one after another. It |
| 90 | * depicts size of block of registers for programming each region. |
| 91 | */ |
| 92 | #define TZC_400_REGION_SIZE 0x20 |
| 93 | #define TZC_400_ACTION_OFF 0x4 |
Dan Handley | 7607676 | 2015-03-19 19:26:52 +0000 | [diff] [blame] | 94 | |
| 95 | #ifndef __ASSEMBLY__ |
| 96 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 97 | #include <cdefs.h> |
Dan Handley | 7607676 | 2015-03-19 19:26:52 +0000 | [diff] [blame] | 98 | #include <stdint.h> |
| 99 | |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 100 | /******************************************************************************* |
| 101 | * Function & variable prototypes |
| 102 | ******************************************************************************/ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 103 | void tzc400_init(uintptr_t base); |
| 104 | void tzc400_configure_region0(tzc_region_attributes_t sec_attr, |
| 105 | unsigned int ns_device_access); |
| 106 | void tzc400_configure_region(unsigned int filters, |
| 107 | int region, |
Yatharth Kochar | fc71975 | 2016-04-08 14:40:44 +0100 | [diff] [blame] | 108 | unsigned long long region_base, |
| 109 | unsigned long long region_top, |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 110 | tzc_region_attributes_t sec_attr, |
Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 111 | unsigned int nsaid_permissions); |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 112 | void tzc400_set_action(tzc_action_t action); |
| 113 | void tzc400_enable_filters(void); |
| 114 | void tzc400_disable_filters(void); |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 115 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 116 | static inline void tzc_init(uintptr_t base) |
| 117 | { |
| 118 | tzc400_init(base); |
| 119 | } |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 120 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 121 | static inline void tzc_configure_region0( |
Dan Handley | 53c843a | 2014-08-04 19:53:05 +0100 | [diff] [blame] | 122 | tzc_region_attributes_t sec_attr, |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 123 | unsigned int ns_device_access) |
| 124 | { |
| 125 | tzc400_configure_region0(sec_attr, ns_device_access); |
| 126 | } |
| 127 | |
| 128 | static inline void tzc_configure_region( |
| 129 | unsigned int filters, |
| 130 | int region, |
Yatharth Kochar | fc71975 | 2016-04-08 14:40:44 +0100 | [diff] [blame] | 131 | unsigned long long region_base, |
| 132 | unsigned long long region_top, |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 133 | tzc_region_attributes_t sec_attr, |
| 134 | unsigned int ns_device_access) |
| 135 | { |
| 136 | tzc400_configure_region(filters, region, region_base, |
| 137 | region_top, sec_attr, ns_device_access); |
| 138 | } |
| 139 | |
| 140 | static inline void tzc_set_action(tzc_action_t action) |
| 141 | { |
| 142 | tzc400_set_action(action); |
| 143 | } |
| 144 | |
| 145 | |
| 146 | static inline void tzc_enable_filters(void) |
| 147 | { |
| 148 | tzc400_enable_filters(); |
| 149 | } |
| 150 | |
| 151 | static inline void tzc_disable_filters(void) |
| 152 | { |
| 153 | tzc400_disable_filters(); |
| 154 | } |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 155 | |
Dan Handley | 7607676 | 2015-03-19 19:26:52 +0000 | [diff] [blame] | 156 | #endif /* __ASSEMBLY__ */ |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 157 | |
| 158 | #endif /* __TZC400__ */ |