| Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 1 | /* |
| Varun Wadekar | 0dc9181 | 2015-12-30 15:06:41 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __MEMCTRLV1_H__ |
| 32 | #define __MEMCTRLV1_H__ |
| 33 | |
| 34 | #include <mmio.h> |
| 35 | #include <tegra_def.h> |
| 36 | |
| 37 | /* SMMU registers */ |
| 38 | #define MC_SMMU_CONFIG_0 0x10 |
| 39 | #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 |
| 40 | #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 |
| 41 | #define MC_SMMU_TLB_CONFIG_0 0x14 |
| 42 | #define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 |
| 43 | #define MC_SMMU_PTC_CONFIG_0 0x18 |
| 44 | #define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f |
| 45 | #define MC_SMMU_TLB_FLUSH_0 0x30 |
| 46 | #define TLB_FLUSH_VA_MATCH_ALL 0 |
| 47 | #define TLB_FLUSH_ASID_MATCH_DISABLE 0 |
| 48 | #define TLB_FLUSH_ASID_MATCH_SHIFT 31 |
| 49 | #define MC_SMMU_TLB_FLUSH_ALL \ |
| 50 | (TLB_FLUSH_VA_MATCH_ALL | \ |
| 51 | (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) |
| 52 | #define MC_SMMU_PTC_FLUSH_0 0x34 |
| 53 | #define MC_SMMU_PTC_FLUSH_ALL 0 |
| 54 | #define MC_SMMU_ASID_SECURITY_0 0x38 |
| 55 | #define MC_SMMU_ASID_SECURITY 0 |
| 56 | #define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 |
| 57 | #define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c |
| 58 | #define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 |
| 59 | #define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 |
| 60 | #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 |
| 61 | #define MC_SMMU_TRANSLATION_ENABLE (~0) |
| 62 | |
| 63 | /* TZDRAM carveout configuration registers */ |
| 64 | #define MC_SECURITY_CFG0_0 0x70 |
| 65 | #define MC_SECURITY_CFG1_0 0x74 |
| 66 | |
| 67 | /* Video Memory carveout configuration registers */ |
| 68 | #define MC_VIDEO_PROTECT_BASE 0x648 |
| 69 | #define MC_VIDEO_PROTECT_SIZE_MB 0x64c |
| 70 | |
| 71 | static inline uint32_t tegra_mc_read_32(uint32_t off) |
| 72 | { |
| 73 | return mmio_read_32(TEGRA_MC_BASE + off); |
| 74 | } |
| 75 | |
| 76 | static inline void tegra_mc_write_32(uint32_t off, uint32_t val) |
| 77 | { |
| 78 | mmio_write_32(TEGRA_MC_BASE + off, val); |
| 79 | } |
| 80 | |
| 81 | #endif /* __MEMCTRLV1_H__ */ |