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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32#include <string.h>
33#include <assert.h>
34#include <arch_helpers.h>
35#include <console.h>
36#include <platform.h>
37#include <psci.h>
38#include <psci_private.h>
39
40typedef int (*afflvl_off_handler)(unsigned long, aff_map_node *);
41
42/*******************************************************************************
43 * The next three functions implement a handler for each supported affinity
44 * level which is called when that affinity level is turned off.
45 ******************************************************************************/
46static int psci_afflvl0_off(unsigned long mpidr, aff_map_node *cpu_node)
47{
48 unsigned int index, plat_state;
49 int rc = PSCI_E_SUCCESS;
50 unsigned long sctlr = read_sctlr();
51
52 assert(cpu_node->level == MPIDR_AFFLVL0);
53
Achin Gupta75f73672013-12-05 16:33:10 +000054 /* State management: mark this cpu as turned off */
55 psci_set_state(cpu_node, PSCI_STATE_OFF);
56
Achin Gupta4f6ad662013-10-25 09:08:21 +010057 /*
58 * Generic management: Get the index for clearing any
59 * lingering re-entry information
60 */
61 index = cpu_node->data;
62 memset(&psci_ns_entry_info[index], 0, sizeof(psci_ns_entry_info[index]));
63
64 /*
65 * Arch. management. Perform the necessary steps to flush all
66 * cpu caches.
67 *
68 * TODO: This power down sequence varies across cpus so it needs to be
69 * abstracted out on the basis of the MIDR like in cpu_reset_handler().
70 * Do the bare minimal for the time being. Fix this before porting to
71 * Cortex models.
72 */
73 sctlr &= ~SCTLR_C_BIT;
74 write_sctlr(sctlr);
75
76 /*
77 * CAUTION: This flush to the level of unification makes an assumption
78 * about the cache hierarchy at affinity level 0 (cpu) in the platform.
79 * Ideally the platform should tell psci which levels to flush to exit
80 * coherency.
81 */
82 dcsw_op_louis(DCCISW);
83
84 /*
85 * Plat. management: Perform platform specific actions to turn this
86 * cpu off e.g. exit cpu coherency, program the power controller etc.
87 */
88 if (psci_plat_pm_ops->affinst_off) {
89
90 /* Get the current physical state of this cpu */
Achin Gupta75f73672013-12-05 16:33:10 +000091 plat_state = psci_get_phys_state(cpu_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +010092 rc = psci_plat_pm_ops->affinst_off(mpidr,
93 cpu_node->level,
94 plat_state);
95 }
96
Achin Gupta4f6ad662013-10-25 09:08:21 +010097 return rc;
98}
99
100static int psci_afflvl1_off(unsigned long mpidr, aff_map_node *cluster_node)
101{
102 int rc = PSCI_E_SUCCESS;
103 unsigned int plat_state;
104
105 /* Sanity check the cluster level */
106 assert(cluster_node->level == MPIDR_AFFLVL1);
107
Achin Gupta75f73672013-12-05 16:33:10 +0000108 /* State management: Decrement the cluster reference count */
109 psci_set_state(cluster_node, PSCI_STATE_OFF);
110
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 /*
112 * Keep the physical state of this cluster handy to decide
113 * what action needs to be taken
114 */
Achin Gupta75f73672013-12-05 16:33:10 +0000115 plat_state = psci_get_phys_state(cluster_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116
117 /*
118 * Arch. Management. Flush all levels of caches to PoC if
119 * the cluster is to be shutdown
120 */
121 if (plat_state == PSCI_STATE_OFF)
122 dcsw_op_all(DCCISW);
123
124 /*
Achin Gupta3140a9e2013-12-02 16:23:12 +0000125 * Plat. Management. Allow the platform to do its cluster
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126 * specific bookeeping e.g. turn off interconnect coherency,
127 * program the power controller etc.
128 */
129 if (psci_plat_pm_ops->affinst_off)
130 rc = psci_plat_pm_ops->affinst_off(mpidr,
131 cluster_node->level,
132 plat_state);
133
134 return rc;
135}
136
137static int psci_afflvl2_off(unsigned long mpidr, aff_map_node *system_node)
138{
139 int rc = PSCI_E_SUCCESS;
140 unsigned int plat_state;
141
142 /* Cannot go beyond this level */
143 assert(system_node->level == MPIDR_AFFLVL2);
144
Achin Gupta75f73672013-12-05 16:33:10 +0000145 /* State management: Decrement the system reference count */
146 psci_set_state(system_node, PSCI_STATE_OFF);
147
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148 /*
149 * Keep the physical state of the system handy to decide what
150 * action needs to be taken
151 */
Achin Gupta75f73672013-12-05 16:33:10 +0000152 plat_state = psci_get_phys_state(system_node);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100153
154 /* No arch. and generic bookeeping to do here currently */
155
156 /*
Achin Gupta3140a9e2013-12-02 16:23:12 +0000157 * Plat. Management : Allow the platform to do its bookeeping
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158 * at this affinity level
159 */
160 if (psci_plat_pm_ops->affinst_off)
161 rc = psci_plat_pm_ops->affinst_off(mpidr,
162 system_node->level,
163 plat_state);
164 return rc;
165}
166
167static const afflvl_off_handler psci_afflvl_off_handlers[] = {
168 psci_afflvl0_off,
169 psci_afflvl1_off,
170 psci_afflvl2_off,
171};
172
173/*******************************************************************************
Achin Gupta0959db52013-12-02 17:33:04 +0000174 * This function takes an array of pointers to affinity instance nodes in the
175 * topology tree and calls the off handler for the corresponding affinity
176 * levels
177 ******************************************************************************/
178static int psci_call_off_handlers(mpidr_aff_map_nodes mpidr_nodes,
179 int start_afflvl,
180 int end_afflvl,
181 unsigned long mpidr)
182{
183 int rc = PSCI_E_INVALID_PARAMS, level;
184 aff_map_node *node;
185
186 for (level = start_afflvl; level <= end_afflvl; level++) {
187 node = mpidr_nodes[level];
188 if (node == NULL)
189 continue;
190
191 /*
192 * TODO: In case of an error should there be a way
193 * of restoring what we might have torn down at
194 * lower affinity levels.
195 */
196 rc = psci_afflvl_off_handlers[level](mpidr, node);
197 if (rc != PSCI_E_SUCCESS)
198 break;
199 }
200
201 return rc;
202}
203
204/*******************************************************************************
205 * Top level handler which is called when a cpu wants to power itself down.
206 * It's assumed that along with turning the cpu off, higher affinity levels will
207 * be turned off as far as possible. It traverses through all the affinity
208 * levels performing generic, architectural, platform setup and state management
209 * e.g. for a cluster that's to be powered off, it will call the platform
210 * specific code which will disable coherency at the interconnect level if the
211 * cpu is the last in the cluster. For a cpu it could mean programming the power
212 * the power controller etc.
213 *
214 * The state of all the relevant affinity levels is changed prior to calling the
215 * affinity level specific handlers as their actions would depend upon the state
216 * the affinity level is about to enter.
217 *
218 * The affinity level specific handlers are called in ascending order i.e. from
219 * the lowest to the highest affinity level implemented by the platform because
220 * to turn off affinity level X it is neccesary to turn off affinity level X - 1
221 * first.
222 *
223 * CAUTION: This function is called with coherent stacks so that coherency can
224 * be turned off and caches can be flushed safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225 ******************************************************************************/
226int psci_afflvl_off(unsigned long mpidr,
Achin Gupta0959db52013-12-02 17:33:04 +0000227 int start_afflvl,
228 int end_afflvl)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229{
Achin Gupta0959db52013-12-02 17:33:04 +0000230 int rc = PSCI_E_SUCCESS;
Achin Gupta0959db52013-12-02 17:33:04 +0000231 mpidr_aff_map_nodes mpidr_nodes;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232
233 mpidr &= MPIDR_AFFINITY_MASK;;
234
235 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000236 * Collect the pointers to the nodes in the topology tree for
237 * each affinity instance in the mpidr. If this function does
238 * not return successfully then either the mpidr or the affinity
239 * levels are incorrect. In either case, we cannot return back
240 * to the caller as it would not know what to do.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241 */
Achin Gupta0959db52013-12-02 17:33:04 +0000242 rc = psci_get_aff_map_nodes(mpidr,
243 start_afflvl,
244 end_afflvl,
245 mpidr_nodes);
246 assert (rc == PSCI_E_SUCCESS);
247
Achin Gupta4f6ad662013-10-25 09:08:21 +0100248 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000249 * This function acquires the lock corresponding to each affinity
250 * level so that by the time all locks are taken, the system topology
251 * is snapshot and state management can be done safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252 */
Achin Gupta0959db52013-12-02 17:33:04 +0000253 psci_acquire_afflvl_locks(mpidr,
254 start_afflvl,
255 end_afflvl,
256 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100257
Achin Gupta0959db52013-12-02 17:33:04 +0000258 /* Perform generic, architecture and platform specific handling */
259 rc = psci_call_off_handlers(mpidr_nodes,
260 start_afflvl,
261 end_afflvl,
262 mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100263
264 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000265 * Release the locks corresponding to each affinity level in the
266 * reverse order to which they were acquired.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100267 */
Achin Gupta0959db52013-12-02 17:33:04 +0000268 psci_release_afflvl_locks(mpidr,
269 start_afflvl,
270 end_afflvl,
271 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272
Achin Gupta4f6ad662013-10-25 09:08:21 +0100273 return rc;
274}