developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 1 | /* |
developer | a21d47e | 2019-05-02 19:29:25 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019, MediaTek Inc. All rights reserved. |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <common/bl_common.h> |
Julius Werner | 1f36321 | 2019-05-30 17:34:08 -0700 | [diff] [blame] | 10 | #include <common/desc_image_load.h> |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 11 | #include <plat/common/common_def.h> |
| 12 | #include <drivers/console.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <drivers/generic_delay_timer.h> |
| 15 | #include <mcucfg.h> |
developer | 3f3f1ab | 2019-05-02 22:26:22 +0800 | [diff] [blame] | 16 | #include <mt_gic_v3.h> |
Hung-Te Lin | c05a0b5 | 2019-05-02 21:42:41 +0800 | [diff] [blame] | 17 | #include <lib/coreboot.h> |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 18 | #include <lib/mmio.h> |
| 19 | #include <mtk_plat_common.h> |
developer | a21d47e | 2019-05-02 19:29:25 +0800 | [diff] [blame] | 20 | #include <mtspmc.h> |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 21 | #include <plat_debug.h> |
developer | 092c53a | 2019-05-03 16:59:07 +0800 | [diff] [blame] | 22 | #include <plat_params.h> |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 23 | #include <plat_private.h> |
| 24 | #include <platform_def.h> |
| 25 | #include <scu.h> |
| 26 | #include <drivers/ti/uart/uart_16550.h> |
| 27 | |
| 28 | static entry_point_info_t bl32_ep_info; |
| 29 | static entry_point_info_t bl33_ep_info; |
| 30 | |
| 31 | static void platform_setup_cpu(void) |
| 32 | { |
| 33 | mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); |
| 34 | |
developer | c3af646 | 2019-08-21 21:16:29 +0800 | [diff] [blame] | 35 | /* Mcusys dcm control */ |
| 36 | /* Enable pll plldiv dcm */ |
| 37 | mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, |
| 38 | BUS_PLLDIV_DCM); |
| 39 | mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, |
| 40 | MP0_PLLDIV_DCM); |
| 41 | mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, |
| 42 | MP2_PLLDIV_DCM); |
| 43 | /* Enable mscib dcm */ |
| 44 | mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, |
| 45 | MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL); |
| 46 | mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, |
| 47 | MCSIB_DCM_MASK, MCSIB_DCM); |
| 48 | /* Enable adb400 dcm */ |
| 49 | mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, |
| 50 | CCI_ADB400_DCM_MASK, CCI_ADB400_DCM); |
| 51 | /* Enable bus clock dcm */ |
| 52 | mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, |
| 53 | MCU_BUS_DCM); |
| 54 | /* Enable bus fabric dcm */ |
| 55 | mmio_clrsetbits_32( |
| 56 | (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl, |
| 57 | MCUSYS_BUS_FABRIC_DCM_MASK, |
| 58 | MCUSYS_BUS_FABRIC_DCM); |
| 59 | /* Enable l2c sram dcm */ |
| 60 | mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, |
| 61 | L2C_SRAM_DCM); |
| 62 | /* Enable busmp0 sync dcm */ |
| 63 | mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, |
| 64 | SYNC_DCM_MASK, SYNC_DCM); |
| 65 | /* Enable cntvalue dcm */ |
| 66 | mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, |
| 67 | CNTVALUEB_DCM); |
| 68 | /* Enable dcm cluster stall */ |
| 69 | mmio_clrsetbits_32( |
| 70 | (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, |
| 71 | MCUSYS_MAX_ACCESS_LATENCY_MASK, |
| 72 | MCUSYS_MAX_ACCESS_LATENCY); |
| 73 | mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, |
| 74 | MCU0_SYNC_DCM_STALL_WR_EN); |
| 75 | /* Enable rgu dcm */ |
| 76 | mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, |
| 77 | CPUSYS_RGU_DCM_CINFIG); |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | /******************************************************************************* |
| 81 | * Return a pointer to the 'entry_point_info' structure of the next image for |
| 82 | * the security state specified. BL33 corresponds to the non-secure image type |
| 83 | * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| 84 | * if the image does not exist. |
| 85 | ******************************************************************************/ |
| 86 | entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| 87 | { |
| 88 | entry_point_info_t *next_image_info; |
| 89 | |
| 90 | next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; |
Julius Werner | 1f36321 | 2019-05-30 17:34:08 -0700 | [diff] [blame] | 91 | assert(next_image_info->h.type == PARAM_EP); |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 92 | |
| 93 | /* None of the images on this platform can have 0x0 as the entrypoint */ |
| 94 | if (next_image_info->pc) |
| 95 | return next_image_info; |
| 96 | else |
| 97 | return NULL; |
| 98 | } |
| 99 | |
| 100 | /******************************************************************************* |
| 101 | * Perform any BL31 early platform setup. Here is an opportunity to copy |
| 102 | * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they |
| 103 | * are lost (potentially). This needs to be done before the MMU is initialized |
| 104 | * so that the memory layout can be used while creating page tables. |
| 105 | * BL2 has flushed this information to memory, so we are guaranteed to pick up |
| 106 | * good data. |
| 107 | ******************************************************************************/ |
| 108 | void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 109 | u_register_t arg2, u_register_t arg3) |
| 110 | { |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 111 | static console_16550_t console; |
developer | 3f3f1ab | 2019-05-02 22:26:22 +0800 | [diff] [blame] | 112 | |
developer | 092c53a | 2019-05-03 16:59:07 +0800 | [diff] [blame] | 113 | params_early_setup(arg1); |
| 114 | |
Hung-Te Lin | c05a0b5 | 2019-05-02 21:42:41 +0800 | [diff] [blame] | 115 | #if COREBOOT |
| 116 | if (coreboot_serial.type) |
| 117 | console_16550_register(coreboot_serial.baseaddr, |
| 118 | coreboot_serial.input_hertz, |
| 119 | coreboot_serial.baud, |
| 120 | &console); |
| 121 | #else |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 122 | console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); |
Hung-Te Lin | c05a0b5 | 2019-05-02 21:42:41 +0800 | [diff] [blame] | 123 | #endif |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 124 | |
| 125 | NOTICE("MT8183 bl31_setup\n"); |
| 126 | |
Julius Werner | 1f36321 | 2019-05-30 17:34:08 -0700 | [diff] [blame] | 127 | bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | |
| 131 | /******************************************************************************* |
| 132 | * Perform any BL31 platform setup code |
| 133 | ******************************************************************************/ |
| 134 | void bl31_platform_setup(void) |
| 135 | { |
| 136 | platform_setup_cpu(); |
| 137 | generic_delay_timer_init(); |
developer | 3f3f1ab | 2019-05-02 22:26:22 +0800 | [diff] [blame] | 138 | |
| 139 | /* Initialize the GIC driver, CPU and distributor interfaces */ |
| 140 | mt_gic_driver_init(); |
| 141 | mt_gic_init(); |
developer | 8883743 | 2019-05-02 22:01:39 +0800 | [diff] [blame] | 142 | |
| 143 | /* Init mcsi SF */ |
| 144 | plat_mtk_cci_init_sf(); |
developer | a21d47e | 2019-05-02 19:29:25 +0800 | [diff] [blame] | 145 | |
| 146 | #if SPMC_MODE == 1 |
| 147 | spmc_init(); |
| 148 | #endif |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /******************************************************************************* |
| 152 | * Perform the very early platform specific architectural setup here. At the |
| 153 | * moment this is only intializes the mmu in a quick and dirty way. |
| 154 | ******************************************************************************/ |
| 155 | void bl31_plat_arch_setup(void) |
| 156 | { |
developer | 8883743 | 2019-05-02 22:01:39 +0800 | [diff] [blame] | 157 | plat_mtk_cci_init(); |
| 158 | plat_mtk_cci_enable(); |
| 159 | |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 160 | enable_scu(read_mpidr()); |
| 161 | |
| 162 | plat_configure_mmu_el3(BL_CODE_BASE, |
| 163 | BL_COHERENT_RAM_END - BL_CODE_BASE, |
| 164 | BL_CODE_BASE, |
| 165 | BL_CODE_END, |
| 166 | BL_COHERENT_RAM_BASE, |
| 167 | BL_COHERENT_RAM_END); |
| 168 | } |