Fengquan Chen | 67f11f0 | 2022-08-17 10:42:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | #include <arch_helpers.h> |
| 7 | #include <common/debug.h> |
| 8 | #include <lib/mmio.h> |
| 9 | #include <dfd.h> |
| 10 | #include <mtk_sip_svc.h> |
| 11 | #include <plat_dfd.h> |
| 12 | |
| 13 | static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1, |
| 14 | u_register_t arg2, u_register_t arg3, |
| 15 | void *handle, struct smccc_res *smccc_ret) |
| 16 | { |
| 17 | int ret = MTK_SIP_E_SUCCESS; |
| 18 | |
| 19 | switch (arg0) { |
| 20 | case PLAT_MTK_DFD_SETUP_MAGIC: |
| 21 | INFO("[%s] DFD setup call from kernel\n", __func__); |
| 22 | dfd_setup(arg1, arg2, arg3); |
| 23 | break; |
| 24 | case PLAT_MTK_DFD_READ_MAGIC: |
| 25 | /* only allow to access DFD register base + 0x200 */ |
| 26 | if (arg1 <= 0x200) { |
| 27 | ret = mmio_read_32(MISC1_CFG_BASE + arg1); |
| 28 | } |
| 29 | break; |
| 30 | case PLAT_MTK_DFD_WRITE_MAGIC: |
| 31 | /* only allow to access DFD register base + 0x200 */ |
| 32 | if (arg1 <= 0x200) { |
| 33 | sync_writel(MISC1_CFG_BASE + arg1, arg2); |
| 34 | } |
| 35 | break; |
| 36 | default: |
| 37 | ret = MTK_SIP_E_INVALID_PARAM; |
| 38 | break; |
| 39 | } |
| 40 | |
| 41 | return ret; |
| 42 | } |
| 43 | DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_DFD, dfd_smc_dispatcher); |