developer | a444a20 | 2020-06-15 16:41:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLAT_MTK_LPM_H |
| 8 | #define PLAT_MTK_LPM_H |
| 9 | |
| 10 | #include <lib/psci/psci.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | |
developer | a6d504d | 2021-01-04 00:00:12 +0800 | [diff] [blame^] | 13 | #define MT_IRQ_REMAIN_MAX U(32) |
developer | a444a20 | 2020-06-15 16:41:03 +0800 | [diff] [blame] | 14 | #define MT_IRQ_REMAIN_CAT_LOG BIT(31) |
| 15 | |
| 16 | struct mt_irqremain { |
| 17 | unsigned int count; |
| 18 | unsigned int irqs[MT_IRQ_REMAIN_MAX]; |
| 19 | unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX]; |
| 20 | unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX]; |
| 21 | }; |
| 22 | |
| 23 | #define PLAT_RC_STATUS_READY BIT(0) |
| 24 | #define PLAT_RC_STATUS_FEATURE_EN BIT(1) |
| 25 | #define PLAT_RC_STATUS_UART_NONSLEEP BIT(31) |
| 26 | |
| 27 | struct mt_lpm_tz { |
| 28 | int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state); |
| 29 | int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state); |
| 30 | |
| 31 | int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state); |
| 32 | int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state); |
| 33 | |
| 34 | int (*pwr_cluster_on)(unsigned int cpu, |
| 35 | const psci_power_state_t *state); |
| 36 | int (*pwr_cluster_dwn)(unsigned int cpu, |
| 37 | const psci_power_state_t *state); |
| 38 | |
| 39 | int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state); |
| 40 | int (*pwr_mcusys_on_finished)(unsigned int cpu, |
| 41 | const psci_power_state_t *state); |
| 42 | int (*pwr_mcusys_dwn)(unsigned int cpu, |
| 43 | const psci_power_state_t *state); |
| 44 | }; |
| 45 | |
| 46 | const struct mt_lpm_tz *mt_plat_cpu_pm_init(void); |
| 47 | |
| 48 | #endif /* PLAT_MTK_LPM_H */ |