Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 1 | /* |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 8 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <lib/mmio.h> |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 10 | #include <tegra_def.h> |
| 11 | #include <tegra_platform.h> |
| 12 | #include <tegra_private.h> |
| 13 | |
| 14 | /******************************************************************************* |
| 15 | * Tegra platforms |
| 16 | ******************************************************************************/ |
| 17 | typedef enum tegra_platform { |
| 18 | TEGRA_PLATFORM_SILICON = 0, |
| 19 | TEGRA_PLATFORM_QT, |
| 20 | TEGRA_PLATFORM_FPGA, |
| 21 | TEGRA_PLATFORM_EMULATION, |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 22 | TEGRA_PLATFORM_LINSIM, |
| 23 | TEGRA_PLATFORM_UNIT_FPGA, |
| 24 | TEGRA_PLATFORM_VIRT_DEV_KIT, |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 25 | TEGRA_PLATFORM_MAX, |
| 26 | } tegra_platform_t; |
| 27 | |
| 28 | /******************************************************************************* |
| 29 | * Tegra macros defining all the SoC minor versions |
| 30 | ******************************************************************************/ |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 31 | #define TEGRA_MINOR_QT U(0) |
| 32 | #define TEGRA_MINOR_FPGA U(1) |
| 33 | #define TEGRA_MINOR_ASIM_QT U(2) |
| 34 | #define TEGRA_MINOR_ASIM_LINSIM U(3) |
| 35 | #define TEGRA_MINOR_DSIM_ASIM_LINSIM U(4) |
| 36 | #define TEGRA_MINOR_UNIT_FPGA U(5) |
| 37 | #define TEGRA_MINOR_VIRT_DEV_KIT U(6) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 38 | |
| 39 | /******************************************************************************* |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 40 | * Tegra macros defining all the SoC pre_si_platform |
| 41 | ******************************************************************************/ |
| 42 | #define TEGRA_PRE_SI_QT U(1) |
| 43 | #define TEGRA_PRE_SI_FPGA U(2) |
| 44 | #define TEGRA_PRE_SI_UNIT_FPGA U(3) |
| 45 | #define TEGRA_PRE_SI_ASIM_QT U(4) |
| 46 | #define TEGRA_PRE_SI_ASIM_LINSIM U(5) |
| 47 | #define TEGRA_PRE_SI_DSIM_ASIM_LINSIM U(6) |
| 48 | #define TEGRA_PRE_SI_VDK U(8) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 49 | |
| 50 | /******************************************************************************* |
| 51 | * Tegra chip ID values |
| 52 | ******************************************************************************/ |
| 53 | typedef enum tegra_chipid { |
| 54 | TEGRA_CHIPID_TEGRA13 = 0x13, |
| 55 | TEGRA_CHIPID_TEGRA21 = 0x21, |
Varun Wadekar | fdcdfe2 | 2017-04-13 14:12:49 -0700 | [diff] [blame] | 56 | TEGRA_CHIPID_TEGRA18 = 0x18, |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 57 | } tegra_chipid_t; |
| 58 | |
| 59 | /* |
| 60 | * Read the chip ID value |
| 61 | */ |
| 62 | static uint32_t tegra_get_chipid(void) |
| 63 | { |
| 64 | return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); |
| 65 | } |
| 66 | |
| 67 | /* |
| 68 | * Read the chip's major version from chip ID value |
| 69 | */ |
Varun Wadekar | fc9b91e | 2017-03-10 09:53:37 -0800 | [diff] [blame] | 70 | uint32_t tegra_get_chipid_major(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 71 | { |
| 72 | return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; |
| 73 | } |
| 74 | |
| 75 | /* |
| 76 | * Read the chip's minor version from the chip ID value |
| 77 | */ |
Varun Wadekar | fc9b91e | 2017-03-10 09:53:37 -0800 | [diff] [blame] | 78 | uint32_t tegra_get_chipid_minor(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 79 | { |
| 80 | return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; |
| 81 | } |
| 82 | |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 83 | /* |
| 84 | * Read the chip's pre_si_platform valus from the chip ID value |
| 85 | */ |
| 86 | static uint32_t tegra_get_chipid_pre_si_platform(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 87 | { |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 88 | return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK; |
| 89 | } |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 90 | |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 91 | bool tegra_chipid_is_t132(void) |
| 92 | { |
| 93 | uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK); |
| 94 | |
| 95 | return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA13); |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 96 | } |
| 97 | |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 98 | bool tegra_chipid_is_t186(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 99 | { |
| 100 | uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; |
| 101 | |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 102 | return (chip_id == TEGRA_CHIPID_TEGRA18); |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 103 | } |
| 104 | |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 105 | bool tegra_chipid_is_t210(void) |
Varun Wadekar | fdcdfe2 | 2017-04-13 14:12:49 -0700 | [diff] [blame] | 106 | { |
| 107 | uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; |
| 108 | |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 109 | return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA21); |
Varun Wadekar | fdcdfe2 | 2017-04-13 14:12:49 -0700 | [diff] [blame] | 110 | } |
| 111 | |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 112 | bool tegra_chipid_is_t210_b01(void) |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 113 | { |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 114 | return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2UL)); |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | /* |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 118 | * Read the chip ID value and derive the platform |
| 119 | */ |
| 120 | static tegra_platform_t tegra_get_platform(void) |
| 121 | { |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 122 | uint32_t major, minor, pre_si_platform; |
| 123 | tegra_platform_t ret; |
| 124 | |
| 125 | /* get the major/minor chip ID values */ |
| 126 | major = tegra_get_chipid_major(); |
| 127 | minor = tegra_get_chipid_minor(); |
| 128 | pre_si_platform = tegra_get_chipid_pre_si_platform(); |
| 129 | |
| 130 | if (major == 0U) { |
| 131 | /* |
| 132 | * The minor version number is used by simulation platforms |
| 133 | */ |
| 134 | switch (minor) { |
| 135 | /* |
| 136 | * Cadence's QuickTurn emulation system is a Solaris-based |
| 137 | * chip emulation system |
| 138 | */ |
| 139 | case TEGRA_MINOR_QT: |
| 140 | case TEGRA_MINOR_ASIM_QT: |
| 141 | ret = TEGRA_PLATFORM_QT; |
| 142 | break; |
| 143 | |
| 144 | /* |
| 145 | * FPGAs are used during early software/hardware development |
| 146 | */ |
| 147 | case TEGRA_MINOR_FPGA: |
| 148 | ret = TEGRA_PLATFORM_FPGA; |
| 149 | break; |
| 150 | /* |
| 151 | * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel |
| 152 | * simulation framework. |
| 153 | */ |
| 154 | case TEGRA_MINOR_ASIM_LINSIM: |
| 155 | case TEGRA_MINOR_DSIM_ASIM_LINSIM: |
| 156 | ret = TEGRA_PLATFORM_LINSIM; |
| 157 | break; |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 158 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 159 | /* |
| 160 | * Unit FPGAs run the actual hardware block IP on the FPGA with |
| 161 | * the other parts of the system using Linsim. |
| 162 | */ |
| 163 | case TEGRA_MINOR_UNIT_FPGA: |
| 164 | ret = TEGRA_PLATFORM_UNIT_FPGA; |
| 165 | break; |
| 166 | /* |
| 167 | * The Virtualizer Development Kit (VDK) is the standard chip |
| 168 | * development from Synopsis. |
| 169 | */ |
| 170 | case TEGRA_MINOR_VIRT_DEV_KIT: |
| 171 | ret = TEGRA_PLATFORM_VIRT_DEV_KIT; |
| 172 | break; |
Marvin Hsu | 589a7e1 | 2017-04-12 20:40:27 +0800 | [diff] [blame] | 173 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 174 | default: |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 175 | ret = TEGRA_PLATFORM_MAX; |
| 176 | break; |
| 177 | } |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 178 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 179 | } else if (pre_si_platform > 0U) { |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 180 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 181 | switch (pre_si_platform) { |
| 182 | /* |
| 183 | * Cadence's QuickTurn emulation system is a Solaris-based |
| 184 | * chip emulation system |
| 185 | */ |
| 186 | case TEGRA_PRE_SI_QT: |
| 187 | case TEGRA_PRE_SI_ASIM_QT: |
| 188 | ret = TEGRA_PLATFORM_QT; |
| 189 | break; |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 190 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 191 | /* |
| 192 | * FPGAs are used during early software/hardware development |
| 193 | */ |
| 194 | case TEGRA_PRE_SI_FPGA: |
| 195 | ret = TEGRA_PLATFORM_FPGA; |
| 196 | break; |
| 197 | /* |
| 198 | * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel |
| 199 | * simulation framework. |
| 200 | */ |
| 201 | case TEGRA_PRE_SI_ASIM_LINSIM: |
| 202 | case TEGRA_PRE_SI_DSIM_ASIM_LINSIM: |
| 203 | ret = TEGRA_PLATFORM_LINSIM; |
| 204 | break; |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 205 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 206 | /* |
| 207 | * Unit FPGAs run the actual hardware block IP on the FPGA with |
| 208 | * the other parts of the system using Linsim. |
| 209 | */ |
| 210 | case TEGRA_PRE_SI_UNIT_FPGA: |
| 211 | ret = TEGRA_PLATFORM_UNIT_FPGA; |
| 212 | break; |
| 213 | /* |
| 214 | * The Virtualizer Development Kit (VDK) is the standard chip |
| 215 | * development from Synopsis. |
| 216 | */ |
| 217 | case TEGRA_PRE_SI_VDK: |
| 218 | ret = TEGRA_PLATFORM_VIRT_DEV_KIT; |
| 219 | break; |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 220 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 221 | default: |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 222 | ret = TEGRA_PLATFORM_MAX; |
| 223 | break; |
| 224 | } |
| 225 | |
| 226 | } else { |
| 227 | /* Actual silicon platforms have a non-zero major version */ |
| 228 | ret = TEGRA_PLATFORM_SILICON; |
| 229 | } |
| 230 | |
| 231 | return ret; |
| 232 | } |
| 233 | |
| 234 | bool tegra_platform_is_silicon(void) |
| 235 | { |
| 236 | return ((tegra_get_platform() == TEGRA_PLATFORM_SILICON) ? true : false); |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 237 | } |
| 238 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 239 | bool tegra_platform_is_qt(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 240 | { |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 241 | return ((tegra_get_platform() == TEGRA_PLATFORM_QT) ? true : false); |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 242 | } |
| 243 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 244 | bool tegra_platform_is_linsim(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 245 | { |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 246 | tegra_platform_t plat = tegra_get_platform(); |
| 247 | |
| 248 | return (((plat == TEGRA_PLATFORM_LINSIM) || |
| 249 | (plat == TEGRA_PLATFORM_UNIT_FPGA)) ? true : false); |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 250 | } |
| 251 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 252 | bool tegra_platform_is_fpga(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 253 | { |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 254 | return ((tegra_get_platform() == TEGRA_PLATFORM_FPGA) ? true : false); |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 255 | } |
| 256 | |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 257 | bool tegra_platform_is_emulation(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 258 | { |
| 259 | return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); |
| 260 | } |
Anthony Zhou | 70262ef | 2017-03-22 14:37:04 +0800 | [diff] [blame] | 261 | |
| 262 | bool tegra_platform_is_unit_fpga(void) |
| 263 | { |
| 264 | return ((tegra_get_platform() == TEGRA_PLATFORM_UNIT_FPGA) ? true : false); |
| 265 | } |
| 266 | |
| 267 | bool tegra_platform_is_virt_dev_kit(void) |
| 268 | { |
| 269 | return ((tegra_get_platform() == TEGRA_PLATFORM_VIRT_DEV_KIT) ? true : false); |
| 270 | } |