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git01.mediatek.com / filogic / atf / a67fa2657a12e9d2d982988f8b693ab3bd135176 / . / plat / rockchip / rk3399 / drivers / dram / dram.c
blob: ddae84d340887139bdbd6085c3303cd2d5508f66 [file] [log] [blame]
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <debug.h>
32#include <mmio.h>
33#include <plat_private.h>
34#include "dram.h"
35#include "dram_spec_timing.h"
36#include "string.h"
37#include "soc.h"
38#include "pmu.h"
39
40#include <delay_timer.h>
41
42#define CTL_TRAINING (1)
43#define PI_TRAINING (!CTL_TRAINING)
44
45#define EN_READ_GATE_TRAINING (1)
46#define EN_CA_TRAINING (0)
47#define EN_WRITE_LEVELING (0)
48#define EN_READ_LEVELING (0)
49#define EN_WDQ_LEVELING (0)
50
51#define ENPER_CS_TRAINING_FREQ (933)
52
53struct pll_div {
54 unsigned int mhz;
55 unsigned int refdiv;
56 unsigned int fbdiv;
57 unsigned int postdiv1;
58 unsigned int postdiv2;
59 unsigned int frac;
60 unsigned int freq;
61};
62
63static const struct pll_div dpll_rates_table[] = {
64
65 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */
66 {.mhz = 933, .refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1},
67 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1},
68 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1},
69 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1},
70 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1},
71 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1},
72 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1},
73 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1},
74 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2},
75};
76
77static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE;
78static struct rk3399_ddr_pctl_regs *const rk3399_ddr_pctl[2] = {
79 (void *)DDRC0_BASE, (void *)DDRC1_BASE
80};
81
82static struct rk3399_ddr_pi_regs *const rk3399_ddr_pi[2] = {
83 (void *)DDRC0_PI_BASE, (void *)DDRC1_PI_BASE
84};
85
86static struct rk3399_ddr_publ_regs *const rk3399_ddr_publ[2] = {
87 (void *)DDRC0_PHY_BASE, (void *)DDRC1_PHY_BASE
88};
89
90struct rk3399_dram_status {
91 uint32_t current_index;
92 uint32_t index_freq[2];
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]93 uint32_t low_power_stat;
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]94 struct timing_related_config timing_config;
95 struct drv_odt_lp_config drv_odt_lp_cfg;
96};
97
98static struct rk3399_dram_status rk3399_dram_status;
99static struct ddr_dts_config_timing dts_parameter = {
100 .available = 0
101};
102
103static struct rk3399_sdram_default_config ddr3_default_config = {
104 .bl = 8,
105 .ap = 0,
106 .dramds = 40,
107 .dramodt = 120,
108 .burst_ref_cnt = 1,
109 .zqcsi = 0
110};
111
112static struct drv_odt_lp_config ddr3_drv_odt_default_config = {
113 .ddr3_speed_bin = DDR3_DEFAULT,
114 .pd_idle = 0,
115 .sr_idle = 0,
116 .sr_mc_gate_idle = 0,
117 .srpd_lite_idle = 0,
118 .standby_idle = 0,
119
120 .ddr3_dll_dis_freq = 300,
121 .phy_dll_dis_freq = 125,
122 .odt_dis_freq = 933,
123
124 .dram_side_drv = 40,
125 .dram_side_dq_odt = 120,
126 .dram_side_ca_odt = 120,
127
128 .phy_side_ca_drv = 40,
129 .phy_side_ck_cs_drv = 40,
130 .phy_side_dq_drv = 40,
131 .phy_side_odt = 240,
132};
133
134static struct rk3399_sdram_default_config lpddr3_default_config = {
135 .bl = 8,
136 .ap = 0,
137 .dramds = 34,
138 .dramodt = 240,
139 .burst_ref_cnt = 1,
140 .zqcsi = 0
141};
142
143static struct drv_odt_lp_config lpddr3_drv_odt_default_config = {
144 .ddr3_speed_bin = DDR3_DEFAULT,
145 .pd_idle = 0,
146 .sr_idle = 0,
147 .sr_mc_gate_idle = 0,
148 .srpd_lite_idle = 0,
149 .standby_idle = 0,
150
151 .ddr3_dll_dis_freq = 300,
152 .phy_dll_dis_freq = 125,
153 .odt_dis_freq = 666,
154
155 .dram_side_drv = 40,
156 .dram_side_dq_odt = 120,
157 .dram_side_ca_odt = 120,
158
159 .phy_side_ca_drv = 40,
160 .phy_side_ck_cs_drv = 40,
161 .phy_side_dq_drv = 40,
162 .phy_side_odt = 240,
163};
164
165static struct rk3399_sdram_default_config lpddr4_default_config = {
166 .bl = 16,
167 .ap = 0,
168 .dramds = 40,
169 .dramodt = 240,
170 .caodt = 240,
171 .burst_ref_cnt = 1,
172 .zqcsi = 0
173};
174
175static struct drv_odt_lp_config lpddr4_drv_odt_default_config = {
176 .ddr3_speed_bin = DDR3_DEFAULT,
177 .pd_idle = 0,
178 .sr_idle = 0,
179 .sr_mc_gate_idle = 0,
180 .srpd_lite_idle = 0,
181 .standby_idle = 0,
182
183 .ddr3_dll_dis_freq = 300,
184 .phy_dll_dis_freq = 125,
185 .odt_dis_freq = 933,
186
187 .dram_side_drv = 60,
188 .dram_side_dq_odt = 40,
189 .dram_side_ca_odt = 40,
190
191 .phy_side_ca_drv = 40,
192 .phy_side_ck_cs_drv = 80,
193 .phy_side_dq_drv = 80,
194 .phy_side_odt = 60,
195};
196
197uint32_t dcf_code[] = {
198#include "dcf_code.inc"
199};
200
201
202#define write_32(addr, value)\
203 mmio_write_32((uintptr_t)(addr), (uint32_t)(value))
204
205#define read_32(addr) \
206 mmio_read_32((uintptr_t)(addr))
207#define clrbits_32(addr, clear)\
208 mmio_clrbits_32((uintptr_t)(addr), (uint32_t)(clear))
209#define setbits_32(addr, set)\
210 mmio_setbits_32((uintptr_t)(addr), (uint32_t)(set))
211#define clrsetbits_32(addr, clear, set)\
212 mmio_clrsetbits_32((uintptr_t)(addr), (uint32_t)(clear),\
213 (uint32_t)(set))
214
215#define DCF_START_ADDR (SRAM_BASE + 0x1400)
216#define DCF_PARAM_ADDR (SRAM_BASE + 0x1000)
217
218/* DCF_PAMET */
219#define PARAM_DRAM_FREQ (0)
220#define PARAM_DPLL_CON0 (4)
221#define PARAM_DPLL_CON1 (8)
222#define PARAM_DPLL_CON2 (0xc)
223#define PARAM_DPLL_CON3 (0x10)
224#define PARAM_DPLL_CON4 (0x14)
225#define PARAM_DPLL_CON5 (0x18)
226/* equal to fn<<4 */
227#define PARAM_FREQ_SELECT (0x1c)
228
229static unsigned int get_cs_die_capability(struct rk3399_sdram_config
230 *psdram_config, unsigned int channel,
231 unsigned int cs)
232{
233 unsigned int die;
234 unsigned int cs_cap;
235 unsigned int row[2];
236
237 row[0] = psdram_config->ch[channel].cs0_row;
238 row[1] = psdram_config->ch[channel].cs1_row;
239 die = psdram_config->ch[channel].bus_width /
240 psdram_config->ch[channel].each_die_bus_width;
241 cs_cap = (1 << (row[cs] +
242 (psdram_config->ch[channel].bank / 4 + 1) +
243 psdram_config->ch[channel].col +
244 (psdram_config->ch[channel].bus_width / 16)));
245 if (psdram_config->ch[channel].each_die_6gb_or_12gb)
246 cs_cap = cs_cap * 3 / 4;
247
248 return (cs_cap / die);
249}
250
251static void sdram_config_init(struct rk3399_sdram_config *psdram_config)
252{
253 uint32_t os_reg2_val, i;
254
255 os_reg2_val = read_32(PMUGRF_BASE + PMUGRF_OSREG(2));
256
257 for (i = 0; i < READ_CH_CNT(os_reg2_val); i++) {
258 psdram_config->ch[i].bank = 1 << READ_BK_INFO(os_reg2_val, i);
259 psdram_config->ch[i].bus_width =
260 8 * (1 << READ_BW_INFO(os_reg2_val, i));
261 psdram_config->ch[i].col = READ_COL_INFO(os_reg2_val, i);
262 psdram_config->ch[i].cs0_row =
263 READ_CS0_ROW_INFO(os_reg2_val, i);
264 psdram_config->ch[i].cs1_row =
265 READ_CS1_ROW_INFO(os_reg2_val, i);
266 psdram_config->ch[i].cs_cnt = READ_CS_INFO(os_reg2_val, i);
267 psdram_config->ch[i].each_die_6gb_or_12gb =
268 READ_CH_ROW_INFO(os_reg2_val, i);
269 psdram_config->ch[i].each_die_bus_width =
270 8 * (1 << READ_DIE_BW_INFO(os_reg2_val, i));
271 }
272 psdram_config->dramtype = READ_DRAMTYPE_INFO(os_reg2_val);
273 psdram_config->channal_num = READ_CH_CNT(os_reg2_val);
274}
275
276static void drv_odt_lp_cfg_init(uint32_t dram_type,
277 struct ddr_dts_config_timing *dts_timing,
278 struct drv_odt_lp_config *drv_config)
279{
280 if ((dts_timing) && (dts_timing->available)) {
281 drv_config->ddr3_speed_bin = dts_timing->ddr3_speed_bin;
282 drv_config->pd_idle = dts_timing->pd_idle;
283 drv_config->sr_idle = dts_timing->sr_idle;
284 drv_config->sr_mc_gate_idle = dts_timing->sr_mc_gate_idle;
285 drv_config->srpd_lite_idle = dts_timing->srpd_lite_idle;
286 drv_config->standby_idle = dts_timing->standby_idle;
287 drv_config->ddr3_dll_dis_freq = dts_timing->ddr3_dll_dis_freq;
288 drv_config->phy_dll_dis_freq = dts_timing->phy_dll_dis_freq;
289 }
290
291 switch (dram_type) {
292 case DDR3:
293 if ((dts_timing) && (dts_timing->available)) {
294 drv_config->odt_dis_freq =
295 dts_timing->ddr3_odt_dis_freq;
296 drv_config->dram_side_drv = dts_timing->ddr3_drv;
297 drv_config->dram_side_dq_odt = dts_timing->ddr3_odt;
298 drv_config->phy_side_ca_drv =
299 dts_timing->phy_ddr3_ca_drv;
300 drv_config->phy_side_ck_cs_drv =
301 dts_timing->phy_ddr3_ca_drv;
302 drv_config->phy_side_dq_drv =
303 dts_timing->phy_ddr3_dq_drv;
304 drv_config->phy_side_odt = dts_timing->phy_ddr3_odt;
305 } else {
306 memcpy(drv_config, &ddr3_drv_odt_default_config,
307 sizeof(struct drv_odt_lp_config));
308 }
309 break;
310 case LPDDR3:
311 if ((dts_timing) && (dts_timing->available)) {
312 drv_config->odt_dis_freq =
313 dts_timing->lpddr3_odt_dis_freq;
314 drv_config->dram_side_drv = dts_timing->lpddr3_drv;
315 drv_config->dram_side_dq_odt = dts_timing->lpddr3_odt;
316 drv_config->phy_side_ca_drv =
317 dts_timing->phy_lpddr3_ca_drv;
318 drv_config->phy_side_ck_cs_drv =
319 dts_timing->phy_lpddr3_ca_drv;
320 drv_config->phy_side_dq_drv =
321 dts_timing->phy_lpddr3_dq_drv;
322 drv_config->phy_side_odt = dts_timing->phy_lpddr3_odt;
323
324 } else {
325 memcpy(drv_config, &lpddr3_drv_odt_default_config,
326 sizeof(struct drv_odt_lp_config));
327 }
328 break;
329 case LPDDR4:
330 default:
331 if ((dts_timing) && (dts_timing->available)) {
332 drv_config->odt_dis_freq =
333 dts_timing->lpddr4_odt_dis_freq;
334 drv_config->dram_side_drv = dts_timing->lpddr4_drv;
335 drv_config->dram_side_dq_odt =
336 dts_timing->lpddr4_dq_odt;
337 drv_config->dram_side_ca_odt =
338 dts_timing->lpddr4_ca_odt;
339 drv_config->phy_side_ca_drv =
340 dts_timing->phy_lpddr4_ca_drv;
341 drv_config->phy_side_ck_cs_drv =
342 dts_timing->phy_lpddr4_ck_cs_drv;
343 drv_config->phy_side_dq_drv =
344 dts_timing->phy_lpddr4_dq_drv;
345 drv_config->phy_side_odt = dts_timing->phy_lpddr4_odt;
346 } else {
347 memcpy(drv_config, &lpddr4_drv_odt_default_config,
348 sizeof(struct drv_odt_lp_config));
349 }
350 break;
351 }
352
353 switch (drv_config->phy_side_ca_drv) {
354 case 240:
355 drv_config->phy_side_ca_drv = PHY_DRV_ODT_240;
356 break;
357 case 120:
358 drv_config->phy_side_ca_drv = PHY_DRV_ODT_120;
359 break;
360 case 80:
361 drv_config->phy_side_ca_drv = PHY_DRV_ODT_80;
362 break;
363 case 60:
364 drv_config->phy_side_ca_drv = PHY_DRV_ODT_60;
365 break;
366 case 48:
367 drv_config->phy_side_ca_drv = PHY_DRV_ODT_48;
368 break;
369 case 40:
370 drv_config->phy_side_ca_drv = PHY_DRV_ODT_40;
371 break;
372 default:
373 drv_config->phy_side_ca_drv = PHY_DRV_ODT_34_3;
374 break;
375 };
376
377 switch (drv_config->phy_side_ck_cs_drv) {
378 case 240:
379 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_240;
380 break;
381 case 120:
382 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_120;
383 break;
384 case 80:
385 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_80;
386 break;
387 case 60:
388 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_60;
389 break;
390 case 48:
391 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_48;
392 break;
393 case 40:
394 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_40;
395 break;
396 default:
397 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_34_3;
398 break;
399 }
400
401 switch (drv_config->phy_side_dq_drv) {
402 case 240:
403 drv_config->phy_side_dq_drv = PHY_DRV_ODT_240;
404 break;
405 case 120:
406 drv_config->phy_side_dq_drv = PHY_DRV_ODT_120;
407 break;
408 case 80:
409 drv_config->phy_side_dq_drv = PHY_DRV_ODT_80;
410 break;
411 case 60:
412 drv_config->phy_side_dq_drv = PHY_DRV_ODT_60;
413 break;
414 case 48:
415 drv_config->phy_side_dq_drv = PHY_DRV_ODT_48;
416 break;
417 case 40:
418 drv_config->phy_side_dq_drv = PHY_DRV_ODT_40;
419 break;
420 default:
421 drv_config->phy_side_dq_drv = PHY_DRV_ODT_34_3;
422 break;
423 }
424
425 switch (drv_config->phy_side_odt) {
426 case 240:
427 drv_config->phy_side_odt = PHY_DRV_ODT_240;
428 break;
429 case 120:
430 drv_config->phy_side_odt = PHY_DRV_ODT_120;
431 break;
432 case 80:
433 drv_config->phy_side_odt = PHY_DRV_ODT_80;
434 break;
435 case 60:
436 drv_config->phy_side_odt = PHY_DRV_ODT_60;
437 break;
438 case 48:
439 drv_config->phy_side_odt = PHY_DRV_ODT_48;
440 break;
441 case 40:
442 drv_config->phy_side_odt = PHY_DRV_ODT_40;
443 break;
444 default:
445 drv_config->phy_side_odt = PHY_DRV_ODT_34_3;
446 break;
447 }
448}
449
450static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config,
451 struct rk3399_sdram_config *psdram_config,
452 struct drv_odt_lp_config *drv_config)
453{
454 uint32_t i, j;
455
456 for (i = 0; i < psdram_config->channal_num; i++) {
457 ptiming_config->dram_info[i].speed_rate =
458 drv_config->ddr3_speed_bin;
459 ptiming_config->dram_info[i].cs_cnt =
460 psdram_config->ch[i].cs_cnt;
461 for (j = 0; j < psdram_config->ch[i].cs_cnt; j++) {
462 ptiming_config->dram_info[i].per_die_capability[j] =
463 get_cs_die_capability(psdram_config, i, j);
464 }
465 }
466 ptiming_config->dram_type = psdram_config->dramtype;
467 ptiming_config->ch_cnt = psdram_config->channal_num;
468 switch (psdram_config->dramtype) {
469 case DDR3:
470 ptiming_config->bl = ddr3_default_config.bl;
471 ptiming_config->ap = ddr3_default_config.ap;
472 break;
473 case LPDDR3:
474 ptiming_config->bl = lpddr3_default_config.bl;
475 ptiming_config->ap = lpddr3_default_config.ap;
476 break;
477 case LPDDR4:
478 ptiming_config->bl = lpddr4_default_config.bl;
479 ptiming_config->ap = lpddr4_default_config.ap;
480 ptiming_config->rdbi = 0;
481 ptiming_config->wdbi = 0;
482 break;
483 }
484 ptiming_config->dramds = drv_config->dram_side_drv;
485 ptiming_config->dramodt = drv_config->dram_side_dq_odt;
486 ptiming_config->caodt = drv_config->dram_side_ca_odt;
487}
488
489struct lat_adj_pair {
490 uint32_t cl;
491 uint32_t rdlat_adj;
492 uint32_t cwl;
493 uint32_t wrlat_adj;
494};
495
496const struct lat_adj_pair ddr3_lat_adj[] = {
497 {6, 5, 5, 4},
498 {8, 7, 6, 5},
499 {10, 9, 7, 6},
500 {11, 9, 8, 7},
501 {13, 0xb, 9, 8},
502 {14, 0xb, 0xa, 9}
503};
504
505const struct lat_adj_pair lpddr3_lat_adj[] = {
506 {3, 2, 1, 0},
507 {6, 5, 3, 2},
508 {8, 7, 4, 3},
509 {9, 8, 5, 4},
510 {10, 9, 6, 5},
511 {11, 9, 6, 5},
512 {12, 0xa, 6, 5},
513 {14, 0xc, 8, 7},
514 {16, 0xd, 8, 7}
515};
516
517const struct lat_adj_pair lpddr4_lat_adj[] = {
518 {6, 5, 4, 2},
519 {10, 9, 6, 4},
520 {14, 0xc, 8, 6},
521 {20, 0x11, 0xa, 8},
522 {24, 0x15, 0xc, 0xa},
523 {28, 0x18, 0xe, 0xc},
524 {32, 0x1b, 0x10, 0xe},
525 {36, 0x1e, 0x12, 0x10}
526};
527
528static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl)
529{
530 const struct lat_adj_pair *p;
531 uint32_t cnt;
532 uint32_t i;
533
534 if (dram_type == DDR3) {
535 p = ddr3_lat_adj;
536 cnt = ARRAY_SIZE(ddr3_lat_adj);
537 } else if (dram_type == LPDDR3) {
538 p = lpddr3_lat_adj;
539 cnt = ARRAY_SIZE(lpddr3_lat_adj);
540 } else {
541 p = lpddr4_lat_adj;
542 cnt = ARRAY_SIZE(lpddr4_lat_adj);
543 }
544
545 for (i = 0; i < cnt; i++) {
546 if (cl == p[i].cl)
547 return p[i].rdlat_adj;
548 }
549 /* fail */
550 return 0xff;
551}
552
553static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl)
554{
555 const struct lat_adj_pair *p;
556 uint32_t cnt;
557 uint32_t i;
558
559 if (dram_type == DDR3) {
560 p = ddr3_lat_adj;
561 cnt = ARRAY_SIZE(ddr3_lat_adj);
562 } else if (dram_type == LPDDR3) {
563 p = lpddr3_lat_adj;
564 cnt = ARRAY_SIZE(lpddr3_lat_adj);
565 } else {
566 p = lpddr4_lat_adj;
567 cnt = ARRAY_SIZE(lpddr4_lat_adj);
568 }
569
570 for (i = 0; i < cnt; i++) {
571 if (cwl == p[i].cwl)
572 return p[i].wrlat_adj;
573 }
574 /* fail */
575 return 0xff;
576}
577
578#define PI_REGS_DIMM_SUPPORT (0)
579#define PI_ADD_LATENCY (0)
580#define PI_DOUBLEFREEK (1)
581
582#define PI_PAD_DELAY_PS_VALUE (1000)
583#define PI_IE_ENABLE_VALUE (3000)
584#define PI_TSEL_ENABLE_VALUE (700)
585
586static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing)
587{
588 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */
589 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder,
590 extra_adder, tsel_enable;
591
592 ie_enable = PI_IE_ENABLE_VALUE;
593 tsel_enable = PI_TSEL_ENABLE_VALUE;
594
595 rdlat = pdram_timing->cl + PI_ADD_LATENCY;
596 delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
597 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
598 delay_adder++;
599 hs_offset = 0;
600 tsel_adder = 0;
601 extra_adder = 0;
602 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */
603 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz);
604 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0)
605 tsel_adder++;
606 delay_adder = delay_adder - 1;
607 if (tsel_adder > delay_adder)
608 extra_adder = tsel_adder - delay_adder;
609 else
610 extra_adder = 0;
611 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK)
612 hs_offset = 2;
613 else
614 hs_offset = 1;
615
616 if (delay_adder > (rdlat - 1 - hs_offset)) {
617 rdlat = rdlat - tsel_adder;
618 } else {
619 if ((rdlat - delay_adder) < 2)
620 rdlat = 2;
621 else
622 rdlat = rdlat - delay_adder - extra_adder;
623 }
624
625 return rdlat;
626}
627
628static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing,
629 struct timing_related_config *timing_config)
630{
631 uint32_t tmp;
632
633 if (timing_config->dram_type == LPDDR3) {
634 tmp = pdram_timing->cl;
635 if (tmp >= 14)
636 tmp = 8;
637 else if (tmp >= 10)
638 tmp = 6;
639 else if (tmp == 9)
640 tmp = 5;
641 else if (tmp == 8)
642 tmp = 4;
643 else if (tmp == 6)
644 tmp = 3;
645 else
646 tmp = 1;
647 } else {
648 tmp = 1;
649 }
650
651 return tmp;
652}
653
654static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing,
655 struct timing_related_config *timing_config)
656{
657 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1;
658}
659
660static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing,
661 struct timing_related_config *timing_config)
662{
663 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */
664 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder;
665 uint32_t mem_delay_ps, round_trip_ps;
666 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay;
667
668 ie_enable = PI_IE_ENABLE_VALUE;
669
670 delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
671 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
672 delay_adder++;
673 delay_adder = delay_adder - 1;
674 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK)
675 hs_offset = 2;
676 else
677 hs_offset = 1;
678
679 cas_lat = pdram_timing->cl + PI_ADD_LATENCY;
680
681 if (delay_adder > (cas_lat - 1 - hs_offset)) {
682 ie_delay_adder = 0;
683 } else {
684 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
685 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
686 ie_delay_adder++;
687 }
688
689 if (timing_config->dram_type == DDR3) {
690 mem_delay_ps = 0;
691 } else if (timing_config->dram_type == LPDDR4) {
692 mem_delay_ps = 3600;
693 } else if (timing_config->dram_type == LPDDR3) {
694 mem_delay_ps = 5500;
695 } else {
696 printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n");
697 return 0;
698 }
699 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600;
700 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz);
701 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0)
702 delay_adder++;
703
704 phy_internal_delay = 5 + 2 + 4;
705 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz);
706 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0)
707 lpddr_adder++;
708 dfi_adder = 0;
709 phy_internal_delay = phy_internal_delay + 2;
710 rdlat_delay = delay_adder + phy_internal_delay +
711 ie_delay_adder + lpddr_adder + dfi_adder;
712
713 rdlat_delay = rdlat_delay + 2;
714 return rdlat_delay;
715}
716
717static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing,
718 struct timing_related_config *timing_config)
719{
720 uint32_t tmp, todtoff_min_ps;
721
722 if (timing_config->dram_type == LPDDR3)
723 todtoff_min_ps = 2500;
724 else if (timing_config->dram_type == LPDDR4)
725 todtoff_min_ps = 1500;
726 else
727 todtoff_min_ps = 0;
728 /* todtoff_min */
729 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz);
730 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0)
731 tmp++;
732 return tmp;
733}
734
735static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing,
736 struct timing_related_config *timing_config)
737{
738 uint32_t tmp, todtoff_max_ps;
739
740 if ((timing_config->dram_type == LPDDR4)
741 || (timing_config->dram_type == LPDDR3))
742 todtoff_max_ps = 3500;
743 else
744 todtoff_max_ps = 0;
745
746 /* todtoff_max */
747 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz);
748 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0)
749 tmp++;
750 return tmp;
751}
752
753static void gen_rk3399_ctl_params_f0(struct timing_related_config
754 *timing_config,
755 struct dram_timing_t *pdram_timing)
756{
757 uint32_t i;
758 uint32_t tmp, tmp1;
759
760 for (i = 0; i < timing_config->ch_cnt; i++) {
761 if (timing_config->dram_type == DDR3) {
762 tmp = ((700000 + 10) * timing_config->freq +
763 999) / 1000;
764 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
765 pdram_timing->tmod + pdram_timing->tzqinit;
766 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], tmp);
767
768 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[22],
769 0xffff, pdram_timing->tdllk);
770
771 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32],
772 (pdram_timing->tmod << 8) |
773 pdram_timing->tmrd);
774
775 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59],
776 0xffff << 16,
777 (pdram_timing->txsr -
778 pdram_timing->trcd) << 16);
779 } else if (timing_config->dram_type == LPDDR4) {
780 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5],
781 pdram_timing->tinit1 + pdram_timing->tinit3);
782 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32],
783 (pdram_timing->tmrd << 8) |
784 pdram_timing->tmrd);
785 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59],
786 0xffff << 16, pdram_timing->txsr << 16);
787 } else {
788 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5],
789 pdram_timing->tinit1);
790 write_32(&rk3399_ddr_pctl[i]->denali_ctl[7],
791 pdram_timing->tinit4);
792 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32],
793 (pdram_timing->tmrd << 8) |
794 pdram_timing->tmrd);
795 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59],
796 0xffff << 16, pdram_timing->txsr << 16);
797 }
798 write_32(&rk3399_ddr_pctl[i]->denali_ctl[6],
799 pdram_timing->tinit3);
800 write_32(&rk3399_ddr_pctl[i]->denali_ctl[8],
801 pdram_timing->tinit5);
802 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[23], (0x7f << 16),
803 ((pdram_timing->cl * 2) << 16));
804 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[23], (0x1f << 24),
805 (pdram_timing->cwl << 24));
806 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], 0x3f,
807 pdram_timing->al);
808 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[26], 0xffff << 16,
809 (pdram_timing->trc << 24) |
810 (pdram_timing->trrd << 16));
811 write_32(&rk3399_ddr_pctl[i]->denali_ctl[27],
812 (pdram_timing->tfaw << 24) |
813 (pdram_timing->trppb << 16) |
814 (pdram_timing->twtr << 8) | pdram_timing->tras_min);
815
816 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[31], 0xff << 24,
817 max(4, pdram_timing->trtp) << 24);
818 write_32(&rk3399_ddr_pctl[i]->denali_ctl[33],
819 (pdram_timing->tcke << 24) | pdram_timing->tras_max);
820 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 0xff,
821 max(1, pdram_timing->tckesr));
822 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[39],
823 (0x3f << 16) | (0xff << 8),
824 (pdram_timing->twr << 16) |
825 (pdram_timing->trcd << 8));
826 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[42], 0x1f << 16,
827 pdram_timing->tmrz << 16);
828 tmp = pdram_timing->tdal ? pdram_timing->tdal :
829 (pdram_timing->twr + pdram_timing->trp);
830 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[44], 0xff, tmp);
831 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[45], 0xff,
832 pdram_timing->trp);
833 write_32(&rk3399_ddr_pctl[i]->denali_ctl[48],
834 ((pdram_timing->trefi - 8) << 16) |
835 pdram_timing->trfc);
836 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[52], 0xffff,
837 pdram_timing->txp);
838 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[53], 0xffff << 16,
839 pdram_timing->txpdll << 16);
840 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xf << 24,
841 pdram_timing->tcscke << 24);
842 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xff,
843 pdram_timing->tmrri);
844 write_32(&rk3399_ddr_pctl[i]->denali_ctl[56],
845 (pdram_timing->tzqcke << 24) |
846 (pdram_timing->tmrwckel << 16) |
847 (pdram_timing->tckehcs << 8) | pdram_timing->tckelcs);
848 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 0xffff,
849 pdram_timing->txsnr);
850 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[62], 0xffff << 16,
851 (pdram_timing->tckehcmd << 24) |
852 (pdram_timing->tckelcmd << 16));
853 write_32(&rk3399_ddr_pctl[i]->denali_ctl[63],
854 (pdram_timing->tckelpd << 24) |
855 (pdram_timing->tescke << 16) |
856 (pdram_timing->tsr << 8) | pdram_timing->tckckel);
857 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[64], 0xfff,
858 (pdram_timing->tcmdcke << 8) |
859 pdram_timing->tcsckeh);
860 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[92],
861 (0xffff << 8),
862 (pdram_timing->tcksrx << 16) |
863 (pdram_timing->tcksre << 8));
864 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[108], (0x1 << 24),
865 (timing_config->dllbp << 24));
866 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[122],
867 (0x3FF << 16),
868 (pdram_timing->tvrcg_enable << 16));
869 write_32(&rk3399_ddr_pctl[i]->denali_ctl[123],
870 (pdram_timing->tfc_long << 16) |
871 pdram_timing->tvrcg_disable);
872 write_32(&rk3399_ddr_pctl[i]->denali_ctl[124],
873 (pdram_timing->tvref_long << 16) |
874 (pdram_timing->tckfspx << 8) |
875 pdram_timing->tckfspe);
876 write_32(&rk3399_ddr_pctl[i]->denali_ctl[133],
877 (pdram_timing->mr[1] << 16) | pdram_timing->mr[0]);
878 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[134], 0xffff,
879 pdram_timing->mr[2]);
880 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[138], 0xffff,
881 pdram_timing->mr[3]);
882 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[139], 0xff << 24,
883 pdram_timing->mr11 << 24);
884 write_32(&rk3399_ddr_pctl[i]->denali_ctl[147],
885 (pdram_timing->mr[1] << 16) | pdram_timing->mr[0]);
886 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[148], 0xffff,
887 pdram_timing->mr[2]);
888 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[152], 0xffff,
889 pdram_timing->mr[3]);
890 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[153], 0xff << 24,
891 pdram_timing->mr11 << 24);
892 if (timing_config->dram_type == LPDDR4) {
893 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[140],
894 0xffff << 16, pdram_timing->mr12 << 16);
895 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[142],
896 0xffff << 16, pdram_timing->mr14 << 16);
897 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[145],
898 0xffff << 16, pdram_timing->mr22 << 16);
899 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[154],
900 0xffff << 16, pdram_timing->mr12 << 16);
901 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[156],
902 0xffff << 16, pdram_timing->mr14 << 16);
903 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[159],
904 0xffff << 16, pdram_timing->mr22 << 16);
905 }
906 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[179], 0xfff << 8,
907 pdram_timing->tzqinit << 8);
908 write_32(&rk3399_ddr_pctl[i]->denali_ctl[180],
909 (pdram_timing->tzqcs << 16) |
910 (pdram_timing->tzqinit / 2));
911 write_32(&rk3399_ddr_pctl[i]->denali_ctl[181],
912 (pdram_timing->tzqlat << 16) | pdram_timing->tzqcal);
913 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[212], 0xff << 8,
914 pdram_timing->todton << 8);
915
916 if (timing_config->odt) {
917 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213],
918 1 << 16);
919 if (timing_config->freq < 400)
920 tmp = 4 << 24;
921 else
922 tmp = 8 << 24;
923 } else {
924 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213],
925 1 << 16);
926 tmp = 2 << 24;
927 }
928
929 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[216],
930 0x1f << 24, tmp);
931 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[221],
932 (0x3 << 16) | (0xf << 8),
933 (pdram_timing->tdqsck << 16) |
934 (pdram_timing->tdqsck_max << 8));
935 tmp =
936 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl)
937 << 8) | get_rdlat_adj(timing_config->dram_type,
938 pdram_timing->cl);
939 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[284], 0xffff,
940 tmp);
941 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[82], 0xffff << 16,
942 (4 * pdram_timing->trefi) << 16);
943
944 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[83], 0xffff,
945 (2 * pdram_timing->trefi) & 0xffff);
946
947 if ((timing_config->dram_type == LPDDR3) ||
948 (timing_config->dram_type == LPDDR4)) {
949 tmp = get_pi_wrlat(pdram_timing, timing_config);
950 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
951 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0;
952 } else {
953 tmp = 0;
954 }
955 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[214], 0x3f << 16,
956 (tmp & 0x3f) << 16);
957
958 if ((timing_config->dram_type == LPDDR3) ||
959 (timing_config->dram_type == LPDDR4)) {
960 /* min_rl_preamble= cl+TDQSCK_MIN-1 */
961 tmp = pdram_timing->cl +
962 get_pi_todtoff_min(pdram_timing, timing_config) - 1;
963 /* todtoff_max */
964 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
965 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0;
966 } else {
967 tmp = pdram_timing->cl - pdram_timing->cwl;
968 }
969 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[215], 0x3f << 8,
970 (tmp & 0x3f) << 8);
971
972 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[275], 0xff << 16,
973 (get_pi_tdfi_phy_rdlat
974 (pdram_timing, timing_config)
975 & 0xff) << 16);
976
977 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[277], 0xffff,
978 (2 * pdram_timing->trefi) & 0xffff);
979
980 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[282], 0xffff,
981 (2 * pdram_timing->trefi) & 0xffff);
982
983 write_32(&rk3399_ddr_pctl[i]->denali_ctl[283],
984 20 * pdram_timing->trefi);
985
986 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */
987 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
988 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
989 tmp1++;
990 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5;
991 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[308], 0x3ff << 16,
992 tmp << 16);
993
994 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */
995 tmp = tmp + 18;
996 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[308], 0x3ff,
997 tmp);
998
999 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */
1000 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config);
1001 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) {
1002 if (tmp1 < 5) {
1003 if (tmp1 == 0)
1004 tmp = 0;
1005 else
1006 tmp = tmp1 - 1;
1007 } else {
1008 tmp = tmp1 - 5;
1009 }
1010 } else {
1011 tmp = tmp1 - 2;
1012 }
1013 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 8,
1014 tmp << 8);
1015
1016 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */
1017 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) &&
1018 (pdram_timing->cl >= 5))
1019 tmp = pdram_timing->cl - 5;
1020 else
1021 tmp = pdram_timing->cl - 2;
1022 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff,
1023 tmp);
1024 }
1025}
1026
1027static void gen_rk3399_ctl_params_f1(struct timing_related_config
1028 *timing_config,
1029 struct dram_timing_t *pdram_timing)
1030{
1031 uint32_t i;
1032 uint32_t tmp, tmp1;
1033
1034 for (i = 0; i < timing_config->ch_cnt; i++) {
1035 if (timing_config->dram_type == DDR3) {
1036 tmp =
1037 ((700000 + 10) * timing_config->freq +
1038 999) / 1000;
1039 tmp +=
1040 pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
1041 pdram_timing->tmod + pdram_timing->tzqinit;
1042 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], tmp);
1043 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[22],
1044 0xffff << 16, pdram_timing->tdllk << 16);
1045 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34],
1046 0xffffff00,
1047 (pdram_timing->tmod << 24) |
1048 (pdram_timing->tmrd << 16) |
1049 (pdram_timing->trtp << 8));
1050 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60],
1051 0xffff << 16,
1052 (pdram_timing->txsr -
1053 pdram_timing->trcd) << 16);
1054 } else if (timing_config->dram_type == LPDDR4) {
1055 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9],
1056 pdram_timing->tinit1 + pdram_timing->tinit3);
1057 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34],
1058 0xffffff00,
1059 (pdram_timing->tmrd << 24) |
1060 (pdram_timing->tmrd << 16) |
1061 (pdram_timing->trtp << 8));
1062 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60],
1063 0xffff << 16, pdram_timing->txsr << 16);
1064 } else {
1065 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9],
1066 pdram_timing->tinit1);
1067 write_32(&rk3399_ddr_pctl[i]->denali_ctl[11],
1068 pdram_timing->tinit4);
1069 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34],
1070 0xffffff00,
1071 (pdram_timing->tmrd << 24) |
1072 (pdram_timing->tmrd << 16) |
1073 (pdram_timing->trtp << 8));
1074 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60],
1075 0xffff << 16, pdram_timing->txsr << 16);
1076 }
1077 write_32(&rk3399_ddr_pctl[i]->denali_ctl[10],
1078 pdram_timing->tinit3);
1079 write_32(&rk3399_ddr_pctl[i]->denali_ctl[12],
1080 pdram_timing->tinit5);
1081 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], (0x7f << 8),
1082 ((pdram_timing->cl * 2) << 8));
1083 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], (0x1f << 16),
1084 (pdram_timing->cwl << 16));
1085 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], 0x3f << 24,
1086 pdram_timing->al << 24);
1087 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[28], 0xffffff00,
1088 (pdram_timing->tras_min << 24) |
1089 (pdram_timing->trc << 16) |
1090 (pdram_timing->trrd << 8));
1091 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[29], 0xffffff,
1092 (pdram_timing->tfaw << 16) |
1093 (pdram_timing->trppb << 8) | pdram_timing->twtr);
1094 write_32(&rk3399_ddr_pctl[i]->denali_ctl[35],
1095 (pdram_timing->tcke << 24) | pdram_timing->tras_max);
1096 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[36], 0xff,
1097 max(1, pdram_timing->tckesr));
1098 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[39],
1099 (0xff << 24), (pdram_timing->trcd << 24));
1100 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[40],
1101 0x3f, pdram_timing->twr);
1102 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[42], 0x1f << 24,
1103 pdram_timing->tmrz << 24);
1104 tmp = pdram_timing->tdal ? pdram_timing->tdal :
1105 (pdram_timing->twr + pdram_timing->trp);
1106 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[44], 0xff << 8,
1107 tmp << 8);
1108 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[45], 0xff << 8,
1109 pdram_timing->trp << 8);
1110 write_32(&rk3399_ddr_pctl[i]->denali_ctl[49],
1111 ((pdram_timing->trefi - 8) << 16) |
1112 pdram_timing->trfc);
1113 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[52], 0xffff << 16,
1114 pdram_timing->txp << 16);
1115 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[54], 0xffff,
1116 pdram_timing->txpdll);
1117 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xff << 8,
1118 pdram_timing->tmrri << 8);
1119 write_32(&rk3399_ddr_pctl[i]->denali_ctl[57],
1120 (pdram_timing->tmrwckel << 24) |
1121 (pdram_timing->tckehcs << 16) |
1122 (pdram_timing->tckelcs << 8) | pdram_timing->tcscke);
1123 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[58], 0xf,
1124 pdram_timing->tzqcke);
1125 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[61], 0xffff,
1126 pdram_timing->txsnr);
1127 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[64], 0xffff << 16,
1128 (pdram_timing->tckehcmd << 24) |
1129 (pdram_timing->tckelcmd << 16));
1130 write_32(&rk3399_ddr_pctl[i]->denali_ctl[65],
1131 (pdram_timing->tckelpd << 24) |
1132 (pdram_timing->tescke << 16) |
1133 (pdram_timing->tsr << 8) | pdram_timing->tckckel);
1134 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[66], 0xfff,
1135 (pdram_timing->tcmdcke << 8) |
1136 pdram_timing->tcsckeh);
1137 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[92], (0xff << 24),
1138 (pdram_timing->tcksre << 24));
1139 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[93], 0xff,
1140 pdram_timing->tcksrx);
1141 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[108], (0x1 << 25),
1142 (timing_config->dllbp << 25));
1143 write_32(&rk3399_ddr_pctl[i]->denali_ctl[125],
1144 (pdram_timing->tvrcg_disable << 16) |
1145 pdram_timing->tvrcg_enable);
1146 write_32(&rk3399_ddr_pctl[i]->denali_ctl[126],
1147 (pdram_timing->tckfspx << 24) |
1148 (pdram_timing->tckfspe << 16) |
1149 pdram_timing->tfc_long);
1150 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[127], 0xffff,
1151 pdram_timing->tvref_long);
1152 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[134],
1153 0xffff << 16, pdram_timing->mr[0] << 16);
1154 write_32(&rk3399_ddr_pctl[i]->denali_ctl[135],
1155 (pdram_timing->mr[2] << 16) | pdram_timing->mr[1]);
1156 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[138],
1157 0xffff << 16, pdram_timing->mr[3] << 16);
1158 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[140], 0xff,
1159 pdram_timing->mr11);
1160 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[148],
1161 0xffff << 16, pdram_timing->mr[0] << 16);
1162 write_32(&rk3399_ddr_pctl[i]->denali_ctl[149],
1163 (pdram_timing->mr[2] << 16) | pdram_timing->mr[1]);
1164 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[152],
1165 0xffff << 16, pdram_timing->mr[3] << 16);
1166 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[154], 0xff,
1167 pdram_timing->mr11);
1168 if (timing_config->dram_type == LPDDR4) {
1169 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[141],
1170 0xffff, pdram_timing->mr12);
1171 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[143],
1172 0xffff, pdram_timing->mr14);
1173 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[146],
1174 0xffff, pdram_timing->mr22);
1175 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[155],
1176 0xffff, pdram_timing->mr12);
1177 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[157],
1178 0xffff, pdram_timing->mr14);
1179 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[160],
1180 0xffff, pdram_timing->mr22);
1181 }
1182 write_32(&rk3399_ddr_pctl[i]->denali_ctl[182],
1183 ((pdram_timing->tzqinit / 2) << 16) |
1184 pdram_timing->tzqinit);
1185 write_32(&rk3399_ddr_pctl[i]->denali_ctl[183],
1186 (pdram_timing->tzqcal << 16) | pdram_timing->tzqcs);
1187 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[184], 0x3f,
1188 pdram_timing->tzqlat);
1189 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[188], 0xfff,
1190 pdram_timing->tzqreset);
1191 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[212], 0xff << 16,
1192 pdram_timing->todton << 16);
1193
1194 if (timing_config->odt) {
1195 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213],
1196 (1 << 24));
1197 if (timing_config->freq < 400)
1198 tmp = 4 << 24;
1199 else
1200 tmp = 8 << 24;
1201 } else {
1202 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213],
1203 (1 << 24));
1204 tmp = 2 << 24;
1205 }
1206 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[217], 0x1f << 24,
1207 tmp);
1208 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[221], 0xf << 24,
1209 (pdram_timing->tdqsck_max << 24));
1210 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[222], 0x3,
1211 pdram_timing->tdqsck);
1212 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[291], 0xffff,
1213 (get_wrlat_adj(timing_config->dram_type,
1214 pdram_timing->cwl) << 8) |
1215 get_rdlat_adj(timing_config->dram_type,
1216 pdram_timing->cl));
1217
1218 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[84], 0xffff,
1219 (4 * pdram_timing->trefi) & 0xffff);
1220
1221 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[84], 0xffff << 16,
1222 ((2 * pdram_timing->trefi) & 0xffff) << 16);
1223
1224 if ((timing_config->dram_type == LPDDR3) ||
1225 (timing_config->dram_type == LPDDR4)) {
1226 tmp = get_pi_wrlat(pdram_timing, timing_config);
1227 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
1228 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0;
1229 } else {
1230 tmp = 0;
1231 }
1232 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[214], 0x3f << 24,
1233 (tmp & 0x3f) << 24);
1234
1235 if ((timing_config->dram_type == LPDDR3) ||
1236 (timing_config->dram_type == LPDDR4)) {
1237 /* min_rl_preamble= cl+TDQSCK_MIN-1 */
1238 tmp = pdram_timing->cl +
1239 get_pi_todtoff_min(pdram_timing, timing_config) - 1;
1240 /* todtoff_max */
1241 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
1242 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0;
1243 } else {
1244 tmp = pdram_timing->cl - pdram_timing->cwl;
1245 }
1246 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[215], 0x3f << 16,
1247 (tmp & 0x3f) << 16);
1248
1249 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[275], 0xff << 24,
1250 (get_pi_tdfi_phy_rdlat
1251 (pdram_timing, timing_config)
1252 & 0xff) << 24);
1253
1254 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[284],
1255 0xffff << 16,
1256 ((2 * pdram_timing->trefi) & 0xffff) << 16);
1257
1258 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[289], 0xffff,
1259 (2 * pdram_timing->trefi) & 0xffff);
1260
1261 write_32(&rk3399_ddr_pctl[i]->denali_ctl[290],
1262 20 * pdram_timing->trefi);
1263
1264 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */
1265 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
1266 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
1267 tmp1++;
1268 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5;
1269 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[309], 0x3ff << 16,
1270 tmp << 16);
1271
1272 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */
1273 tmp = tmp + 18;
1274 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[309], 0x3ff,
1275 tmp);
1276
1277 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */
1278 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config);
1279 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) {
1280 if (tmp1 < 5) {
1281 if (tmp1 == 0)
1282 tmp = 0;
1283 else
1284 tmp = tmp1 - 1;
1285 } else {
1286 tmp = tmp1 - 5;
1287 }
1288 } else {
1289 tmp = tmp1 - 2;
1290 }
1291
1292 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 24,
1293 tmp << 24);
1294
1295 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */
1296 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) &&
1297 (pdram_timing->cl >= 5))
1298 tmp = pdram_timing->cl - 5;
1299 else
1300 tmp = pdram_timing->cl - 2;
1301 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 16,
1302 tmp << 16);
1303 }
1304}
1305
1306static void gen_rk3399_ctl_params(struct timing_related_config *timing_config,
1307 struct dram_timing_t *pdram_timing,
1308 uint32_t fn)
1309{
1310 if (fn == 0)
1311 gen_rk3399_ctl_params_f0(timing_config, pdram_timing);
1312 else
1313 gen_rk3399_ctl_params_f1(timing_config, pdram_timing);
1314
1315#if CTL_TRAINING
1316 uint32_t i, tmp0, tmp1;
1317
1318 tmp0 = tmp1 = 0;
1319#if EN_READ_GATE_TRAINING
1320 tmp1 = 1;
1321#endif
1322
1323#if EN_CA_TRAINING
1324 tmp0 |= (1 << 8);
1325#endif
1326
1327#if EN_WRITE_LEVELING
1328 tmp0 |= (1 << 16);
1329#endif
1330
1331#if EN_READ_LEVELING
1332 tmp0 |= (1 << 24);
1333#endif
1334 for (i = 0; i < timing_config->ch_cnt; i++) {
1335 if (tmp0 | tmp1)
1336 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[305],
1337 1 << 16);
1338 if (tmp0)
1339 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[70], tmp0);
1340 if (tmp1)
1341 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[71], tmp1);
1342 }
1343#endif
1344}
1345
1346static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
1347 struct dram_timing_t *pdram_timing)
1348{
1349 uint32_t tmp, tmp1, tmp2;
1350 uint32_t i;
1351
1352 for (i = 0; i < timing_config->ch_cnt; i++) {
1353 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */
1354 tmp = 4 * pdram_timing->trefi;
1355 write_32(&rk3399_ddr_pi[i]->denali_pi[2], tmp);
1356 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */
1357 tmp = 2 * pdram_timing->trefi;
1358 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[3], 0xffff, tmp);
1359 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */
1360 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[7], 0xffff << 16,
1361 tmp << 16);
1362
1363 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */
1364 if (timing_config->dram_type == LPDDR4)
1365 tmp = 2;
1366 else
1367 tmp = 0;
1368 tmp = (pdram_timing->bl / 2) + 4 +
1369 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp +
1370 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config);
1371 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[42], 0xff, tmp);
1372 /* PI_43 PI_WRLAT_F0:RW:0:5 */
1373 if (timing_config->dram_type == LPDDR3) {
1374 tmp = get_pi_wrlat(pdram_timing, timing_config);
1375 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x1f,
1376 tmp);
1377 }
1378 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */
1379 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x3f << 8,
1380 PI_ADD_LATENCY << 8);
1381
1382 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */
1383 tmp = pdram_timing->cl * 2;
1384 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x7f << 16,
1385 tmp << 16);
1386 /* PI_46 PI_TREF_F0:RW:16:16 */
1387 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[46], 0xffff << 16,
1388 pdram_timing->trefi << 16);
1389 /* PI_46 PI_TRFC_F0:RW:0:10 */
1390 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[46], 0x3ff,
1391 pdram_timing->trfc);
1392 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */
1393 if (timing_config->dram_type == LPDDR3) {
1394 tmp = get_pi_todtoff_max(pdram_timing, timing_config);
1395 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[66],
1396 0xff << 24, tmp << 24);
1397 }
1398 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */
1399 if ((timing_config->dram_type == LPDDR3) ||
1400 (timing_config->dram_type == LPDDR4)) {
1401 tmp1 = get_pi_wrlat(pdram_timing, timing_config);
1402 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1403 if (tmp1 > tmp2)
1404 tmp = tmp1 - tmp2;
1405 else
1406 tmp = 0;
1407 } else if (timing_config->dram_type == DDR3) {
1408 tmp = 0;
1409 }
1410 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[72], 0x3f << 16,
1411 tmp << 16);
1412 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */
1413 if ((timing_config->dram_type == LPDDR3) ||
1414 (timing_config->dram_type == LPDDR4)) {
1415 /* min_rl_preamble= cl+TDQSCK_MIN-1 */
1416 tmp1 = pdram_timing->cl +
1417 get_pi_todtoff_min(pdram_timing, timing_config) - 1;
1418 /* todtoff_max */
1419 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1420 if (tmp1 > tmp2)
1421 tmp = tmp1 - tmp2;
1422 else
1423 tmp = 0;
1424 } else if (timing_config->dram_type == DDR3) {
1425 tmp = pdram_timing->cl - pdram_timing->cwl;
1426 }
1427 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[73], 0x3f << 8,
1428 tmp << 8);
1429 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */
1430 tmp = get_pi_rdlat_adj(pdram_timing);
1431 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[89], 0xff << 16,
1432 tmp << 16);
1433 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */
1434 tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
1435 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[90], 0xff << 16,
1436 tmp << 16);
1437 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */
1438 tmp1 = tmp;
1439 if (tmp1 < 5) {
1440 if (tmp1 == 0)
1441 tmp = 0;
1442 else
1443 tmp = tmp1 - 1;
1444 } else {
1445 tmp = tmp1 - 5;
1446 }
1447 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[91], 0xff << 16,
1448 tmp << 16);
1449 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */
1450 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
1451 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
1452 tmp1++;
1453 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5;
1454 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[95], 0x3ff << 16,
1455 tmp << 16);
1456 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */
1457 tmp = tmp + 18;
1458 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[95], 0x3ff, tmp);
1459 /* PI_102 PI_TMRZ_F0:RW:8:5 */
1460 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[102], 0x1f << 8,
1461 pdram_timing->tmrz << 8);
1462 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */
1463 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz);
1464 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0)
1465 tmp1++;
1466 /* pi_tdfi_calvl_strobe=tds_train+5 */
1467 tmp = tmp1 + 5;
1468 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[111], 0xf << 8,
1469 tmp << 8);
1470 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */
1471 tmp = 10000 / (1000000 / pdram_timing->mhz);
1472 if ((10000 % (1000000 / pdram_timing->mhz)) != 0)
1473 tmp++;
1474 if (pdram_timing->mhz <= 100)
1475 tmp = tmp + 1;
1476 else
1477 tmp = tmp + 8;
1478 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[116], 0x3f << 16,
1479 tmp << 16);
1480 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */
1481 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[125], 0xffff << 8,
1482 pdram_timing->mr[1] << 8);
1483 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */
1484 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[133], 0xffff,
1485 pdram_timing->mr[1]);
1486 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */
1487 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[140], 0xffff << 16,
1488 pdram_timing->mr[1] << 16);
1489 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */
1490 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[148], 0xffff,
1491 pdram_timing->mr[1]);
1492 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */
1493 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[126], 0xffff,
1494 pdram_timing->mr[2]);
1495 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */
1496 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[133], 0xffff << 16,
1497 pdram_timing->mr[2] << 16);
1498 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */
1499 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[141], 0xffff,
1500 pdram_timing->mr[2]);
1501 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */
1502 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[148], 0xffff << 16,
1503 pdram_timing->mr[2] << 16);
1504 /* PI_156 PI_TFC_F0:RW:0:10 */
1505 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[156], 0x3ff,
1506 pdram_timing->trfc);
1507 /* PI_158 PI_TWR_F0:RW:24:6 */
1508 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0x3f << 24,
1509 pdram_timing->twr << 24);
1510 /* PI_158 PI_TWTR_F0:RW:16:6 */
1511 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0x3f << 16,
1512 pdram_timing->twtr << 16);
1513 /* PI_158 PI_TRCD_F0:RW:8:8 */
1514 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0xff << 8,
1515 pdram_timing->trcd << 8);
1516 /* PI_158 PI_TRP_F0:RW:0:8 */
1517 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0xff,
1518 pdram_timing->trp);
1519 /* PI_157 PI_TRTP_F0:RW:24:8 */
1520 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[157], 0xff << 24,
1521 pdram_timing->trtp << 24);
1522 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */
1523 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[159], 0xff << 24,
1524 pdram_timing->tras_min << 24);
1525 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */
1526 tmp = pdram_timing->tras_max * 99 / 100;
1527 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[159], 0x1ffff, tmp);
1528 /* PI_160 PI_TMRD_F0:RW:16:6 */
1529 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[160], 0x3f << 16,
1530 pdram_timing->tmrd << 16);
1531 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */
1532 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[160], 0xf,
1533 pdram_timing->tdqsck_max);
1534 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */
1535 tmp = 2 * pdram_timing->trefi;
1536 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[187], 0xffff << 8,
1537 tmp << 8);
1538 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */
1539 tmp = 20 * pdram_timing->trefi;
1540 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[188], 0xffffffff,
1541 tmp);
1542 }
1543}
1544
1545static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
1546 struct dram_timing_t *pdram_timing)
1547{
1548 uint32_t tmp, tmp1, tmp2;
1549 uint32_t i;
1550
1551 for (i = 0; i < timing_config->ch_cnt; i++) {
1552 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */
1553 tmp = 4 * pdram_timing->trefi;
1554 write_32(&rk3399_ddr_pi[i]->denali_pi[4], tmp);
1555 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */
1556 tmp = 2 * pdram_timing->trefi;
1557 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[5], 0xffff, tmp);
1558 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */
1559 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[12], 0xffff, tmp);
1560
1561 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */
1562 if (timing_config->dram_type == LPDDR4)
1563 tmp = 2;
1564 else
1565 tmp = 0;
1566 tmp = (pdram_timing->bl / 2) + 4 +
1567 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp +
1568 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config);
1569 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[42], 0xff << 8,
1570 tmp << 8);
1571 /* PI_43 PI_WRLAT_F1:RW:24:5 */
1572 if (timing_config->dram_type == LPDDR3) {
1573 tmp = get_pi_wrlat(pdram_timing, timing_config);
1574 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43],
1575 0x1f << 24, tmp << 24);
1576 }
1577 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */
1578 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[44], 0x3f,
1579 PI_ADD_LATENCY);
1580 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */
1581 tmp = pdram_timing->cl * 2;
1582 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[44], 0x7f << 8,
1583 tmp << 8);
1584 /* PI_47 PI_TREF_F1:RW:16:16 */
1585 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[47], 0xffff << 16,
1586 pdram_timing->trefi << 16);
1587 /* PI_47 PI_TRFC_F1:RW:0:10 */
1588 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[47], 0x3ff,
1589 pdram_timing->trfc);
1590 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */
1591 if (timing_config->dram_type == LPDDR3) {
1592 tmp = get_pi_todtoff_max(pdram_timing, timing_config);
1593 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[67],
1594 0xff << 8, tmp << 8);
1595 }
1596 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */
1597 if ((timing_config->dram_type == LPDDR3)
1598 || (timing_config->dram_type == LPDDR4)) {
1599 tmp1 = get_pi_wrlat(pdram_timing, timing_config);
1600 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1601 if (tmp1 > tmp2)
1602 tmp = tmp1 - tmp2;
1603 else
1604 tmp = 0;
1605 } else if (timing_config->dram_type == DDR3) {
1606 tmp = 0;
1607 }
1608 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[72], 0x3f << 24,
1609 tmp << 24);
1610 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */
1611 if ((timing_config->dram_type == LPDDR3)
1612 || (timing_config->dram_type == LPDDR4)) {
1613 /* min_rl_preamble= cl+TDQSCK_MIN-1 */
1614 tmp1 =
1615 pdram_timing->cl + get_pi_todtoff_min(pdram_timing,
1616 timing_config)
1617 - 1;
1618 /* todtoff_max */
1619 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1620 if (tmp1 > tmp2)
1621 tmp = tmp1 - tmp2;
1622 else
1623 tmp = 0;
1624 } else if (timing_config->dram_type == DDR3) {
1625 tmp = pdram_timing->cl - pdram_timing->cwl;
1626 }
1627 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[73], 0x3f << 16,
1628 tmp << 16);
1629 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */
1630 tmp = get_pi_rdlat_adj(pdram_timing);
1631 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[89], 0xff << 24,
1632 tmp << 24);
1633 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */
1634 tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
1635 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[90], 0xff << 24,
1636 tmp << 24);
1637 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */
1638 tmp1 = tmp;
1639 if (tmp1 < 5) {
1640 if (tmp1 == 0)
1641 tmp = 0;
1642 else
1643 tmp = tmp1 - 1;
1644 } else {
1645 tmp = tmp1 - 5;
1646 }
1647 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[91], 0xff << 24,
1648 tmp << 24);
1649 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */
1650 /* tadr=20ns */
1651 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
1652 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
1653 tmp1++;
1654 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5;
1655 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[96], 0x3ff << 16,
1656 tmp << 16);
1657 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */
1658 tmp = tmp + 18;
1659 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[96], 0x3ff, tmp);
1660 /*PI_103 PI_TMRZ_F1:RW:0:5 */
1661 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[103], 0x1f,
1662 pdram_timing->tmrz);
1663 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */
1664 /* tds_train=ceil(2/ns) */
1665 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz);
1666 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0)
1667 tmp1++;
1668 /* pi_tdfi_calvl_strobe=tds_train+5 */
1669 tmp = tmp1 + 5;
1670 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[111], 0xf << 16,
1671 tmp << 16);
1672 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */
1673 tmp = 10000 / (1000000 / pdram_timing->mhz);
1674 if ((10000 % (1000000 / pdram_timing->mhz)) != 0)
1675 tmp++;
1676 if (pdram_timing->mhz <= 100)
1677 tmp = tmp + 1;
1678 else
1679 tmp = tmp + 8;
1680 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[116], 0x3f << 24,
1681 tmp << 24);
1682 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */
1683 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[128], 0xffff,
1684 pdram_timing->mr[1]);
1685 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */
1686 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[135], 0xffff << 8,
1687 pdram_timing->mr[1] << 8);
1688 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */
1689 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[143], 0xffff,
1690 pdram_timing->mr[1]);
1691 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */
1692 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[150], 0xffff << 8,
1693 pdram_timing->mr[1] << 8);
1694 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */
1695 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[128], 0xffff << 16,
1696 pdram_timing->mr[2] << 16);
1697 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */
1698 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[136], 0xffff,
1699 pdram_timing->mr[2]);
1700 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */
1701 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[143], 0xffff << 16,
1702 pdram_timing->mr[2] << 16);
1703 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */
1704 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[151], 0xffff,
1705 pdram_timing->mr[2]);
1706 /* PI_156 PI_TFC_F1:RW:16:10 */
1707 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[156], 0x3ff << 16,
1708 pdram_timing->trfc << 16);
1709 /* PI_162 PI_TWR_F1:RW:8:6 */
1710 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[162], 0x3f << 8,
1711 pdram_timing->twr << 8);
1712 /* PI_162 PI_TWTR_F1:RW:0:6 */
1713 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[162], 0x3f,
1714 pdram_timing->twtr);
1715 /* PI_161 PI_TRCD_F1:RW:24:8 */
1716 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 24,
1717 pdram_timing->trcd << 24);
1718 /* PI_161 PI_TRP_F1:RW:16:8 */
1719 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 16,
1720 pdram_timing->trp << 16);
1721 /* PI_161 PI_TRTP_F1:RW:8:8 */
1722 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 8,
1723 pdram_timing->trtp << 8);
1724 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */
1725 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[163], 0xff << 24,
1726 pdram_timing->tras_min << 24);
1727 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */
1728 tmp = pdram_timing->tras_max * 99 / 100;
1729 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[163], 0x1ffff, tmp);
1730 /* PI_164 PI_TMRD_F1:RW:16:6 */
1731 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[164], 0x3f << 16,
1732 pdram_timing->tmrd << 16);
1733 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */
1734 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[164], 0xf,
1735 pdram_timing->tdqsck_max);
1736 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */
1737 tmp = 2 * pdram_timing->trefi;
1738 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[189], 0xffff, tmp);
1739 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */
1740 tmp = 20 * pdram_timing->trefi;
1741 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[190], 0xffffffff,
1742 tmp);
1743 }
1744}
1745
1746static void gen_rk3399_pi_params(struct timing_related_config *timing_config,
1747 struct dram_timing_t *pdram_timing,
1748 uint32_t fn)
1749{
1750 if (fn == 0)
1751 gen_rk3399_pi_params_f0(timing_config, pdram_timing);
1752 else
1753 gen_rk3399_pi_params_f1(timing_config, pdram_timing);
1754
1755#if PI_TRAINING
1756 uint32_t i;
1757
1758 for (i = 0; i < timing_config->ch_cnt; i++) {
1759#if EN_READ_GATE_TRAINING
1760 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[80], 3 << 24,
1761 2 << 24);
1762#endif
1763
1764#if EN_CA_TRAINING
1765 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[100], 3 << 8,
1766 2 << 8);
1767#endif
1768
1769#if EN_WRITE_LEVELING
1770 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[60], 3 << 8,
1771 2 << 8);
1772#endif
1773
1774#if EN_READ_LEVELING
1775 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[80], 3 << 16,
1776 2 << 16);
1777#endif
1778
1779#if EN_WDQ_LEVELING
1780 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[124], 3 << 16,
1781 2 << 16);
1782#endif
1783 }
1784#endif
1785}
1786
1787static void gen_rk3399_set_odt(uint32_t odt_en)
1788{
1789 uint32_t drv_odt_val;
1790 uint32_t i;
1791
1792 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) {
1793 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16;
1794 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[5],
1795 0x7 << 16, drv_odt_val);
1796 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[133],
1797 0x7 << 16, drv_odt_val);
1798 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[261],
1799 0x7 << 16, drv_odt_val);
1800 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[389],
1801 0x7 << 16, drv_odt_val);
1802 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24;
1803 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[6],
1804 0x7 << 24, drv_odt_val);
1805 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[134],
1806 0x7 << 24, drv_odt_val);
1807 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[262],
1808 0x7 << 24, drv_odt_val);
1809 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[390],
1810 0x7 << 24, drv_odt_val);
1811 }
1812}
1813
1814static void gen_rk3399_set_ds_odt(struct timing_related_config *timing_config,
1815 struct drv_odt_lp_config *drv_config)
1816{
1817 uint32_t i, drv_odt_val;
1818
1819 for (i = 0; i < timing_config->ch_cnt; i++) {
1820 if (timing_config->dram_type == LPDDR4)
1821 drv_odt_val = drv_config->phy_side_odt |
1822 (PHY_DRV_ODT_Hi_Z << 4) |
1823 (drv_config->phy_side_dq_drv << 8) |
1824 (drv_config->phy_side_dq_drv << 12);
1825 else if (timing_config->dram_type == LPDDR3)
1826 drv_odt_val = PHY_DRV_ODT_Hi_Z |
1827 (drv_config->phy_side_odt << 4) |
1828 (drv_config->phy_side_dq_drv << 8) |
1829 (drv_config->phy_side_dq_drv << 12);
1830 else
1831 drv_odt_val = drv_config->phy_side_odt |
1832 (drv_config->phy_side_odt << 4) |
1833 (drv_config->phy_side_dq_drv << 8) |
1834 (drv_config->phy_side_dq_drv << 12);
1835
1836 /* DQ drv odt set */
1837 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[6], 0xffffff,
1838 drv_odt_val);
1839 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[134], 0xffffff,
1840 drv_odt_val);
1841 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[262], 0xffffff,
1842 drv_odt_val);
1843 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[390], 0xffffff,
1844 drv_odt_val);
1845 /* DQS drv odt set */
1846 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[7], 0xffffff,
1847 drv_odt_val);
1848 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[135], 0xffffff,
1849 drv_odt_val);
1850 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[263], 0xffffff,
1851 drv_odt_val);
1852 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[391], 0xffffff,
1853 drv_odt_val);
1854
1855 gen_rk3399_set_odt(timing_config->odt);
1856
1857 /* CA drv set */
1858 drv_odt_val = drv_config->phy_side_ca_drv |
1859 (drv_config->phy_side_ca_drv << 4);
1860 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[544], 0xff,
1861 drv_odt_val);
1862 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[672], 0xff,
1863 drv_odt_val);
1864 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[800], 0xff,
1865 drv_odt_val);
1866
1867 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[928], 0xff,
1868 drv_odt_val);
1869 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[937], 0xff,
1870 drv_odt_val);
1871 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[935], 0xff,
1872 drv_odt_val);
1873
1874 drv_odt_val = drv_config->phy_side_ck_cs_drv |
1875 (drv_config->phy_side_ck_cs_drv << 4);
1876 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[929], 0xff,
1877 drv_odt_val);
1878 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[939], 0xff,
1879 drv_odt_val);
1880 }
1881}
1882
1883static void gen_rk3399_phy_params(struct timing_related_config *timing_config,
1884 struct drv_odt_lp_config *drv_config,
1885 struct dram_timing_t *pdram_timing,
1886 uint32_t fn)
1887{
1888 uint32_t tmp, i, div, j;
1889 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps;
1890 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps;
1891 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder;
1892 uint32_t extra_adder, delta, hs_offset;
1893
1894 for (i = 0; i < timing_config->ch_cnt; i++) {
1895
1896 pad_delay_ps = PI_PAD_DELAY_PS_VALUE;
1897 ie_enable = PI_IE_ENABLE_VALUE;
1898 tsel_enable = PI_TSEL_ENABLE_VALUE;
1899
1900 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[896],
1901 (0x3 << 8) | 1, fn << 8);
1902
1903 /* PHY_LOW_FREQ_SEL */
1904 /* DENALI_PHY_913 1bit offset_0 */
1905 if (timing_config->freq > 400)
1906 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[913], 1);
1907 else
1908 setbits_32(&rk3399_ddr_publ[i]->denali_phy[913], 1);
1909
1910 /* PHY_RPTR_UPDATE_x */
1911 /* DENALI_PHY_87/215/343/471 4bit offset_16 */
1912 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3;
1913 if ((2500 % (1000000 / pdram_timing->mhz)) != 0)
1914 tmp++;
1915 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[87], 0xf << 16,
1916 tmp << 16);
1917 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[215], 0xf << 16,
1918 tmp << 16);
1919 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[343], 0xf << 16,
1920 tmp << 16);
1921 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[471], 0xf << 16,
1922 tmp << 16);
1923
1924 /* PHY_PLL_CTRL */
1925 /* DENALI_PHY_911 13bits offset_0 */
1926 /* PHY_LP4_BOOT_PLL_CTRL */
1927 /* DENALI_PHY_919 13bits offset_0 */
1928 if (pdram_timing->mhz <= 150)
1929 tmp = 3;
1930 else if (pdram_timing->mhz <= 300)
1931 tmp = 2;
1932 else if (pdram_timing->mhz <= 600)
1933 tmp = 1;
1934 else
1935 tmp = 0;
1936 tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1);
1937 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[911], 0x1fff,
1938 tmp);
1939 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[919], 0x1fff,
1940 tmp);
1941
1942 /* PHY_PLL_CTRL_CA */
1943 /* DENALI_PHY_911 13bits offset_16 */
1944 /* PHY_LP4_BOOT_PLL_CTRL_CA */
1945 /* DENALI_PHY_919 13bits offset_16 */
1946 if (pdram_timing->mhz <= 150)
1947 tmp = 3;
1948 else if (pdram_timing->mhz <= 300)
1949 tmp = 2;
1950 else if (pdram_timing->mhz <= 600)
1951 tmp = 1;
1952 else
1953 tmp = 0;
1954 tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1);
1955 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[911],
1956 0x1fff << 16, tmp << 16);
1957 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[919],
1958 0x1fff << 16, tmp << 16);
1959
1960 /* PHY_TCKSRE_WAIT */
1961 /* DENALI_PHY_922 4bits offset_24 */
1962 if (pdram_timing->mhz <= 400)
1963 tmp = 1;
1964 else if (pdram_timing->mhz <= 800)
1965 tmp = 3;
1966 else if (pdram_timing->mhz <= 1000)
1967 tmp = 4;
1968 else
1969 tmp = 5;
1970 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[922], 0xf << 24,
1971 tmp << 24);
1972 /* PHY_CAL_CLK_SELECT_0:RW8:3 */
1973 div = pdram_timing->mhz / (2 * 20);
1974 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) {
1975 if (div < j)
1976 break;
1977 }
1978 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[947], 0x7 << 8,
1979 tmp << 8);
1980 setbits_32(&rk3399_ddr_publ[i]->denali_phy[927], (1 << 22));
1981
1982 if (timing_config->dram_type == DDR3) {
1983 mem_delay_ps = 0;
1984 trpre_min_ps = 1000;
1985 } else if (timing_config->dram_type == LPDDR4) {
1986 mem_delay_ps = 1500;
1987 trpre_min_ps = 900;
1988 } else if (timing_config->dram_type == LPDDR3) {
1989 mem_delay_ps = 2500;
1990 trpre_min_ps = 900;
1991 } else {
1992 ERROR("gen_rk3399_phy_params:dramtype unsupport\n");
1993 return;
1994 }
1995 total_delay_ps = mem_delay_ps + pad_delay_ps;
1996 delay_frac_ps =
1997 1000 * total_delay_ps / (1000000 / pdram_timing->mhz);
1998 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2);
1999 gate_delay_frac_ps =
2000 gate_delay_ps - gate_delay_ps / 1000 * 1000;
2001 tmp = gate_delay_frac_ps * 0x200 / 1000;
2002 /* PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY */
2003 /* DENALI_PHY_2/130/258/386 10bits offset_0 */
2004 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[2], 0x2ff, tmp);
2005 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[130], 0x2ff, tmp);
2006 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[258], 0x2ff, tmp);
2007 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[386], 0x2ff, tmp);
2008 /* PHY_RDDQS_GATE_SLAVE_DELAY */
2009 /* DENALI_PHY_77/205/333/461 10bits offset_16 */
2010 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[77], 0x2ff << 16,
2011 tmp << 16);
2012 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[205], 0x2ff << 16,
2013 tmp << 16);
2014 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[333], 0x2ff << 16,
2015 tmp << 16);
2016 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[461], 0x2ff << 16,
2017 tmp << 16);
2018
2019 tmp = gate_delay_ps / 1000;
2020 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */
2021 /* DENALI_PHY_10/138/266/394 4bit offset_0 */
2022 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[10], 0xf, tmp);
2023 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[138], 0xf, tmp);
2024 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[266], 0xf, tmp);
2025 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[394], 0xf, tmp);
2026 /* PHY_RDDQS_LATENCY_ADJUST */
2027 /* DENALI_PHY_78/206/334/462 4bits offset_0 */
2028 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[78], 0xf, tmp);
2029 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[206], 0xf, tmp);
2030 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[334], 0xf, tmp);
2031 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[462], 0xf, tmp);
2032 /* PHY_GTLVL_LAT_ADJ_START */
2033 /* DENALI_PHY_80/208/336/464 4bits offset_16 */
2034 tmp = delay_frac_ps / 1000;
2035 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[80], 0xf << 16,
2036 tmp << 16);
2037 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[208], 0xf << 16,
2038 tmp << 16);
2039 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[336], 0xf << 16,
2040 tmp << 16);
2041 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[464], 0xf << 16,
2042 tmp << 16);
2043
2044 cas_lat = pdram_timing->cl + PI_ADD_LATENCY;
2045 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz);
2046 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
2047 rddata_en_ie_dly++;
2048 rddata_en_ie_dly = rddata_en_ie_dly - 1;
2049 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz);
2050 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0)
2051 tsel_adder++;
2052 if (rddata_en_ie_dly > tsel_adder)
2053 extra_adder = rddata_en_ie_dly - tsel_adder;
2054 else
2055 extra_adder = 0;
2056 delta = cas_lat - rddata_en_ie_dly;
2057 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK)
2058 hs_offset = 2;
2059 else
2060 hs_offset = 1;
2061 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) {
2062 tmp = 0;
2063 } else {
2064 if ((delta == 2) || (delta == 1))
2065 tmp = rddata_en_ie_dly - 0 - extra_adder;
2066 else
2067 tmp = extra_adder;
2068 }
2069 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */
2070 /* DENALI_PHY_9/137/265/393 4bit offset_16 */
2071 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[9], 0xf << 16,
2072 tmp << 16);
2073 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[137], 0xf << 16,
2074 tmp << 16);
2075 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[265], 0xf << 16,
2076 tmp << 16);
2077 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[393], 0xf << 16,
2078 tmp << 16);
2079 /* PHY_RDDATA_EN_TSEL_DLY */
2080 /* DENALI_PHY_86/214/342/470 4bit offset_0 */
2081 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[86], 0xf, tmp);
2082 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[214], 0xf, tmp);
2083 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[342], 0xf, tmp);
2084 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[470], 0xf, tmp);
2085
2086 if (tsel_adder > rddata_en_ie_dly)
2087 extra_adder = tsel_adder - rddata_en_ie_dly;
2088 else
2089 extra_adder = 0;
2090 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset))
2091 tmp = tsel_adder;
2092 else
2093 tmp = rddata_en_ie_dly - 0 + extra_adder;
2094 /* PHY_LP4_BOOT_RDDATA_EN_DLY */
2095 /* DENALI_PHY_9/137/265/393 4bit offset_8 */
2096 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[9], 0xf << 8,
2097 tmp << 8);
2098 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[137], 0xf << 8,
2099 tmp << 8);
2100 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[265], 0xf << 8,
2101 tmp << 8);
2102 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[393], 0xf << 8,
2103 tmp << 8);
2104 /* PHY_RDDATA_EN_DLY */
2105 /* DENALI_PHY_85/213/341/469 4bit offset_24 */
2106 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[85], 0xf << 24,
2107 tmp << 24);
2108 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[213], 0xf << 24,
2109 tmp << 24);
2110 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[341], 0xf << 24,
2111 tmp << 24);
2112 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[469], 0xf << 24,
2113 tmp << 24);
2114
2115 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) {
2116
2117 /*
2118 * Note:Per-CS Training is not compatible at speeds
2119 * under 533 MHz. If the PHY is running at a speed
2120 * less than 533MHz, all phy_per_cs_training_en_X
2121 * parameters must be cleared to 0.
2122 */
2123
2124 /*DENALI_PHY_84/212/340/468 1bit offset_16 */
2125 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[84],
2126 0x1 << 16);
2127 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[212],
2128 0x1 << 16);
2129 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[340],
2130 0x1 << 16);
2131 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[468],
2132 0x1 << 16);
2133 } else {
2134 setbits_32(&rk3399_ddr_publ[i]->denali_phy[84],
2135 0x1 << 16);
2136 setbits_32(&rk3399_ddr_publ[i]->denali_phy[212],
2137 0x1 << 16);
2138 setbits_32(&rk3399_ddr_publ[i]->denali_phy[340],
2139 0x1 << 16);
2140 setbits_32(&rk3399_ddr_publ[i]->denali_phy[468],
2141 0x1 << 16);
2142 }
2143 }
2144}
2145
2146static int to_get_clk_index(unsigned int mhz)
2147{
2148 int pll_cnt, i;
2149
2150 pll_cnt = sizeof(dpll_rates_table) / sizeof(struct pll_div);
2151
2152 /* Assumming rate_table is in descending order */
2153 for (i = 0; i < pll_cnt; i++) {
2154 if (mhz >= dpll_rates_table[i].mhz)
2155 break;
2156 }
2157
2158 return i;
2159}
2160
2161uint32_t rkclk_prepare_pll_timing(unsigned int mhz)
2162{
2163 unsigned int refdiv, postdiv1, fbdiv, postdiv2;
2164 int index;
2165
2166 index = to_get_clk_index(mhz);
2167 refdiv = dpll_rates_table[index].refdiv;
2168 fbdiv = dpll_rates_table[index].fbdiv;
2169 postdiv1 = dpll_rates_table[index].postdiv1;
2170 postdiv2 = dpll_rates_table[index].postdiv2;
2171 write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(fbdiv));
2172 write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON1, POSTDIV2(postdiv2) |
2173 POSTDIV1(postdiv1) | REFDIV(refdiv));
2174 return (24 * fbdiv) / refdiv / postdiv1 / postdiv2;
2175}
2176
2177uint64_t ddr_get_rate(void)
2178{
2179 uint32_t refdiv, postdiv1, fbdiv, postdiv2;
2180
2181 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f;
2182 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff;
2183 postdiv1 =
2184 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7;
2185 postdiv2 =
2186 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7;
2187
2188 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000;
2189}
2190
2191/*
2192 * return: bit12: channel 1, external self-refresh
2193 * bit11: channel 1, stdby_mode
2194 * bit10: channel 1, self-refresh with controller and memory clock gate
2195 * bit9: channel 1, self-refresh
2196 * bit8: channel 1, power-down
2197 *
2198 * bit4: channel 1, external self-refresh
2199 * bit3: channel 0, stdby_mode
2200 * bit2: channel 0, self-refresh with controller and memory clock gate
2201 * bit1: channel 0, self-refresh
2202 * bit0: channel 0, power-down
2203 */
2204uint32_t exit_low_power(void)
2205{
2206 struct rk3399_ddr_pctl_regs *ddr_pctl_regs;
2207 uint32_t low_power = 0;
2208 uint32_t channel_mask;
2209 uint32_t channel;
2210 uint32_t tmp;
2211
2212 channel_mask = (read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 0x3;
2213 for (channel = 0; channel < 2; channel++) {
2214 ddr_pctl_regs = rk3399_ddr_pctl[channel];
2215 if (!(channel_mask & (1 << channel)))
2216 continue;
2217
2218 /* exit stdby mode */
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2219 write_32(&rk3399_ddr_cic->cic_ctrl1,
2220 (1 << (channel + 16)) | (0 << channel));
2221 /* exit external self-refresh */
2222 tmp = channel ? 12 : 8;
2223 low_power |= ((read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 0x1)
2224 << (4 + 8 * channel);
2225 clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp);
2226 while (!(read_32(PMU_BASE + PMU_DDR_SREF_ST) &
2227 (1 << channel)))
2228 ;
2229 /* exit auto low-power */
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2230 clrbits_32(&ddr_pctl_regs->denali_ctl[101], 0x7);
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2231 /* lp_cmd to exit */
2232 if (((read_32(&ddr_pctl_regs->denali_ctl[100]) >> 24) &
2233 0x7f) != 0x40) {
2234 while (read_32(&ddr_pctl_regs->denali_ctl[200]) & 0x1)
2235 ;
2236 clrsetbits_32(&ddr_pctl_regs->denali_ctl[93],
2237 0xff << 24, 0x69 << 24);
2238 while (((read_32(&ddr_pctl_regs->denali_ctl[100]) >>
2239 24) & 0x7f) != 0x40)
2240 ;
2241 }
2242 }
2243 return low_power;
2244}
2245
2246void resume_low_power(uint32_t low_power)
2247{
2248 struct rk3399_ddr_pctl_regs *ddr_pctl_regs;
2249 uint32_t channel_mask;
2250 uint32_t channel;
2251 uint32_t tmp;
2252 uint32_t val;
2253
2254 channel_mask = (read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 0x3;
2255 for (channel = 0; channel < 2; channel++) {
2256 ddr_pctl_regs = rk3399_ddr_pctl[channel];
2257 if (!(channel_mask & (1 << channel)))
2258 continue;
2259
2260 /* resume external self-refresh */
2261 tmp = channel ? 12 : 8;
2262 val = (low_power >> (4 + 8 * channel)) & 0x1;
2263 setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp);
2264 /* resume auto low-power */
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2265 val = (low_power >> (8 * channel)) & 0x7;
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2266 setbits_32(&ddr_pctl_regs->denali_ctl[101], val);
2267 /* resume stdby mode */
2268 val = (low_power >> (3 + 8 * channel)) & 0x1;
2269 write_32(&rk3399_ddr_cic->cic_ctrl1,
2270 (1 << (channel + 16)) | (val << channel));
2271 }
2272}
2273
2274static void wait_dcf_done(void)
2275{
2276 while ((read_32(DCF_BASE + DCF_DCF_ISR) & (DCF_DONE)) == 0)
2277 continue;
2278}
2279
2280void clr_dcf_irq(void)
2281{
2282 /* clear dcf irq status */
2283 mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE);
2284}
2285
2286static void enable_dcf(uint32_t dcf_addr)
2287{
2288 /* config DCF start addr */
2289 write_32(DCF_BASE + DCF_DCF_ADDR, dcf_addr);
2290 /* wait dcf done */
2291 while (read_32(DCF_BASE + DCF_DCF_CTRL) & 1)
2292 continue;
2293 /* clear dcf irq status */
2294 write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE);
2295 /* DCF start */
2296 setbits_32(DCF_BASE + DCF_DCF_CTRL, DCF_START);
2297}
2298
2299void dcf_code_init(void)
2300{
2301 memcpy((void *)DCF_START_ADDR, (void *)dcf_code, sizeof(dcf_code));
2302 /* set dcf master secure */
2303 write_32(SGRF_BASE + 0xe01c, ((0x3 << 0) << 16) | (0 << 0));
2304 write_32(DCF_BASE + DCF_DCF_TOSET, 0x80000000);
2305}
2306
2307static void dcf_start(uint32_t freq, uint32_t index)
2308{
2309 write_32(CRU_BASE + CRU_SOFTRST_CON(10), (0x1 << (1 + 16)) | (1 << 1));
2310 write_32(CRU_BASE + CRU_SOFTRST_CON(11), (0x1 << (0 + 16)) | (1 << 0));
2311 write_32(DCF_PARAM_ADDR + PARAM_FREQ_SELECT, index << 4);
2312
2313 write_32(DCF_PARAM_ADDR + PARAM_DRAM_FREQ, freq);
2314
2315 rkclk_prepare_pll_timing(freq);
2316 udelay(10);
2317 write_32(CRU_BASE + CRU_SOFTRST_CON(10), (0x1 << (1 + 16)) | (0 << 1));
2318 write_32(CRU_BASE + CRU_SOFTRST_CON(11), (0x1 << (0 + 16)) | (0 << 0));
2319 udelay(10);
2320 enable_dcf(DCF_START_ADDR);
2321}
2322
2323static void dram_low_power_config(struct drv_odt_lp_config *lp_config)
2324{
2325 uint32_t tmp, tmp1, i;
2326 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt;
2327 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type;
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2328 uint32_t *low_power = &rk3399_dram_status.low_power_stat;
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2329
2330 if (dram_type == LPDDR4)
2331 tmp = (lp_config->srpd_lite_idle << 16) |
2332 lp_config->pd_idle;
2333 else
2334 tmp = lp_config->pd_idle;
2335
2336 if (dram_type == DDR3)
2337 tmp1 = (2 << 16) | (0x7 << 8) | 7;
2338 else
2339 tmp1 = (3 << 16) | (0x7 << 8) | 7;
2340
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2341 *low_power = 0;
2342
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2343 for (i = 0; i < ch_cnt; i++) {
2344 write_32(&rk3399_ddr_pctl[i]->denali_ctl[102], tmp);
2345 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[103], 0xffff,
2346 (lp_config->sr_mc_gate_idle << 8) |
2347 lp_config->sr_idle);
2348 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[101],
2349 0x70f0f, tmp1);
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2350 *low_power |= (7 << (8 * i));
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2351 }
2352
2353 /* standby idle */
2354 write_32(&rk3399_ddr_cic->cic_idle_th, lp_config->standby_idle);
2355 write_32(&rk3399_ddr_cic->cic_cg_wait_th, 0x640008);
2356
2357 if (ch_cnt == 2) {
2358 write_32(GRF_BASE + GRF_DDRC1_CON1,
2359 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) |
2360 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7)));
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2361 if (lp_config->standby_idle) {
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2362 tmp = 0x002a002a;
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2363 *low_power |= (1 << 11);
2364 } else {
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2365 tmp = 0;
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2366 }
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2367 write_32(&rk3399_ddr_cic->cic_ctrl1, tmp);
2368 }
2369
2370 write_32(GRF_BASE + GRF_DDRC0_CON1,
2371 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) |
2372 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7)));
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2373 if (lp_config->standby_idle) {
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2374 tmp = 0x00150015;
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2375 *low_power |= (1 << 3);
2376 } else {
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2377 tmp = 0;
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2378 }
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2379 write_32(&rk3399_ddr_cic->cic_ctrl1, tmp);
2380}
2381
2382
2383static void dram_related_init(struct ddr_dts_config_timing *dts_timing)
2384{
2385 uint32_t trefi0, trefi1;
2386 uint32_t i;
2387 struct rk3399_sdram_config sdram_config;
2388
2389 dcf_code_init();
2390
2391 /* get sdram config for os reg */
2392 sdram_config_init(&sdram_config);
2393 drv_odt_lp_cfg_init(sdram_config.dramtype, dts_timing,
2394 &rk3399_dram_status.drv_odt_lp_cfg);
2395 sdram_timing_cfg_init(&rk3399_dram_status.timing_config,
2396 &sdram_config,
2397 &rk3399_dram_status.drv_odt_lp_cfg);
2398
2399 trefi0 = ((read_32(&rk3399_ddr_pctl[0]->denali_ctl[48]) >>
2400 16) & 0xffff) + 8;
2401 trefi1 = ((read_32(&rk3399_ddr_pctl[0]->denali_ctl[49]) >>
2402 16) & 0xffff) + 8;
2403
2404 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39;
2405 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39;
2406 rk3399_dram_status.current_index =
2407 (read_32(&rk3399_ddr_pctl[0]->denali_ctl[111])
2408 >> 16) & 0x3;
2409 if (rk3399_dram_status.timing_config.dram_type == DDR3) {
2410 rk3399_dram_status.index_freq[0] /= 2;
2411 rk3399_dram_status.index_freq[1] /= 2;
2412 }
2413 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1)
2414 & 0x1] = 0;
2415
2416 /* disable all training by ctl and pi */
2417 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) {
2418 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[70], (1 << 24) |
2419 (1 << 16) | (1 << 8) | 1);
2420 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[71], 1);
2421
2422 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[60], 0x3 << 8);
2423 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[80], (0x3 << 24) |
2424 (0x3 << 16));
2425 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[100], 0x3 << 8);
2426 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[124], 0x3 << 16);
2427 }
2428
2429 /* init drv odt */
2430 if (rk3399_dram_status.index_freq[rk3399_dram_status.current_index] <
2431 rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq)
2432 rk3399_dram_status.timing_config.odt = 0;
2433 else
2434 rk3399_dram_status.timing_config.odt = 1;
2435 gen_rk3399_set_ds_odt(&rk3399_dram_status.timing_config,
2436 &rk3399_dram_status.drv_odt_lp_cfg);
2437 dram_low_power_config(&rk3399_dram_status.drv_odt_lp_cfg);
2438}
2439
2440static uint32_t prepare_ddr_timing(uint32_t mhz)
2441{
2442 uint32_t index;
2443 struct dram_timing_t dram_timing;
2444
2445 rk3399_dram_status.timing_config.freq = mhz;
2446
2447 if (mhz < rk3399_dram_status.drv_odt_lp_cfg.ddr3_dll_dis_freq)
2448 rk3399_dram_status.timing_config.dllbp = 1;
2449 else
2450 rk3399_dram_status.timing_config.dllbp = 0;
2451 if (mhz < rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) {
2452 rk3399_dram_status.timing_config.odt = 0;
2453 } else {
2454 rk3399_dram_status.timing_config.odt = 1;
2455 gen_rk3399_set_odt(1);
2456 }
2457
2458 index = (rk3399_dram_status.current_index + 1) & 0x1;
2459 if (rk3399_dram_status.index_freq[index] == mhz)
2460 goto out;
2461
2462 /*
2463 * checking if having available gate traiing timing for
2464 * target freq.
2465 */
2466 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing);
2467
2468 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config,
2469 &dram_timing, index);
2470 gen_rk3399_pi_params(&rk3399_dram_status.timing_config,
2471 &dram_timing, index);
2472 gen_rk3399_phy_params(&rk3399_dram_status.timing_config,
2473 &rk3399_dram_status.drv_odt_lp_cfg,
2474 &dram_timing, index);
2475 rk3399_dram_status.index_freq[index] = mhz;
2476
2477
2478out:
2479 return index;
2480}
2481
2482void print_dram_status_info(void)
2483{
2484 uint32_t *p;
2485 uint32_t i;
2486
2487 p = (uint32_t *) &rk3399_dram_status.timing_config;
2488 INFO("rk3399_dram_status.timing_config:\n");
2489 for (i = 0; i < sizeof(struct timing_related_config) / 4; i++)
2490 tf_printf("%u\n", p[i]);
2491 p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg;
2492 INFO("rk3399_dram_status.drv_odt_lp_cfg:\n");
2493 for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++)
2494 tf_printf("%u\n", p[i]);
2495}
2496
2497uint64_t ddr_set_rate(uint64_t hz)
2498{
2499 uint32_t low_power, index;
2500 uint32_t mhz = hz / (1000 * 1000);
2501
2502 if (mhz ==
2503 rk3399_dram_status.index_freq[rk3399_dram_status.current_index])
2504 goto out;
2505
2506 low_power = exit_low_power();
2507 index = prepare_ddr_timing(mhz);
2508 if (index > 1) {
2509 /* set timing error, quit */
2510 mhz = 0;
2511 goto out;
2512 }
2513
2514 dcf_start(mhz, index);
2515 wait_dcf_done();
2516 if (rk3399_dram_status.timing_config.odt == 0)
2517 gen_rk3399_set_odt(0);
2518
2519 rk3399_dram_status.current_index = index;
Caesar Wang853559e2016-08-25 08:38:23 +0800[diff] [blame]2520
2521 if (mhz < dts_parameter.auto_pd_dis_freq)
2522 low_power |= rk3399_dram_status.low_power_stat;
2523
Caesar Wang9740bba2016-08-25 08:37:42 +0800[diff] [blame]2524 resume_low_power(low_power);
2525out:
2526 return mhz;
2527}
2528
2529uint64_t ddr_round_rate(uint64_t hz)
2530{
2531 int index;
2532 uint32_t mhz = hz / (1000 * 1000);
2533
2534 index = to_get_clk_index(mhz);
2535
2536 return dpll_rates_table[index].mhz * 1000 * 1000;
2537}
2538
2539uint64_t dts_timing_receive(uint64_t timing, uint64_t index)
2540{
2541 uint32_t *p = (uint32_t *) &dts_parameter;
2542 static uint32_t receive_nums;
2543
2544 if (index < (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) {
2545 p[index] = (uint32_t)timing;
2546 receive_nums++;
2547 } else {
2548 dts_parameter.available = 0;
2549 return -1;
2550 }
2551
2552 /* receive all parameter */
2553 if (receive_nums == (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) {
2554 dts_parameter.available = 1;
2555 receive_nums = 0;
2556 }
2557
2558 return index;
2559}
2560
2561void ddr_init(void)
2562{
2563 dram_related_init(&dts_parameter);
2564}