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Douglas Raillardd7c21b72017-06-28 15:23:03 +01001ARM CPU Specific Build Macros
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10This document describes the various build options present in the CPU specific
11operations framework to enable errata workarounds and to enable optimizations
12for a specific CPU on a platform.
13
14CPU Errata Workarounds
15----------------------
16
17ARM Trusted Firmware exports a series of build flags which control the
18errata workarounds that are applied to each CPU by the reset handler. The
19errata details can be found in the CPU specific errata documents published
20by ARM:
21
22- `Cortex-A53 MPCore Software Developers Errata Notice`_
23- `Cortex-A57 MPCore Software Developers Errata Notice`_
24
25The errata workarounds are implemented for a particular revision or a set of
26processor revisions. This is checked by the reset handler at runtime. Each
27errata workaround is identified by its ``ID`` as specified in the processor's
28errata notice document. The format of the define used to enable/disable the
29errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
30is for example ``A57`` for the ``Cortex_A57`` CPU.
31
32Refer to the section *CPU errata status reporting* in
33`Firmware Design guide`_ for information on to write errata workaround functions.
34
35All workarounds are disabled by default. The platform is responsible for
36enabling these workarounds according to its requirement by defining the
37errata workaround build flags in the platform specific makefile. In case
38these workarounds are enabled for the wrong CPU revision then the errata
39workaround is not applied. In the DEBUG build, this is indicated by
40printing a warning to the crash console.
41
42In the current implementation, a platform which has more than 1 variant
43with different revisions of a processor has no runtime mechanism available
44for it to specify which errata workarounds should be enabled or not.
45
46The value of the build flags are 0 by default, that is, disabled. Any other
47value will enable it.
48
49For Cortex-A53, following errata build flags are defined :
50
51- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
52 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
53
54- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
55 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
56 r0p4 and onwards, this errata is enabled by default in hardware.
57
58- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
59 CPUs. Though the erratum is present in every revision of the CPU,
60 this workaround is only applied to CPUs from r0p3 onwards, which feature
61 a chicken bit in CPUACTLR\_EL1 to enable a hardware workaround.
62 Earlier revisions of the CPU have other errata which require the same
63 workaround in software, so they should be covered anyway.
64
65For Cortex-A57, following errata build flags are defined :
66
67- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
68 CPU. This needs to be enabled only for revision r0p0 of the CPU.
69
70- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
71 CPU. This needs to be enabled only for revision r0p0 of the CPU.
72
73- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
74 CPU. This needs to be enabled only for revision r0p0 of the CPU.
75
76- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
78
79- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
80 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
81
82- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
83 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
84
85- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
86 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
87
88- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
90
91CPU Specific optimizations
92--------------------------
93
94This section describes some of the optimizations allowed by the CPU micro
95architecture that can be enabled by the platform as desired.
96
97- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
98 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
99 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
100 of the L2 by set/way flushes any dirty lines from the L1 as well. This
101 is a known safe deviation from the Cortex-A57 TRM defined power down
102 sequence. Each Cortex-A57 based platform must make its own decision on
103 whether to use the optimization.
104
105- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
106 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
107 in a way most programmers expect, and will most probably result in a
108 significant speed degradation to any code that employs them. The ARMv8-A
109 architecture (see ARM DDI 0487A.h, section D3.4.3) allows cores to ignore
110 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
111 flag enforces this behaviour. This needs to be enabled only for revisions
112 <= r0p3 of the CPU and is enabled by default.
113
114- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
115 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
116 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
117 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
118 `Cortex-A57 Software Optimization Guide`_.
119
120--------------
121
122*Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.*
123
124.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
125.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf
126.. _Firmware Design guide: firmware-design.rst
127.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf