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Oliver Swede8fed2fe2019-11-11 11:11:06 +00001/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef FPGA_PRIVATE_H
8#define FPGA_PRIVATE_H
9
Javier Almansa Sobrinofc78c3c2020-05-13 14:09:58 +010010#include "../fpga_def.h"
11#include <platform_def.h>
12
13#define C_RUNTIME_READY_KEY (0xaa55aa55)
14#define VALID_MPID (1U)
Andre Przywara01767932020-07-07 10:40:46 +010015#define FPGA_MAX_DTB_SIZE 0x10000
Javier Almansa Sobrinofc78c3c2020-05-13 14:09:58 +010016
17#ifndef __ASSEMBLER__
18
19extern unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT];
Oliver Swede8fed2fe2019-11-11 11:11:06 +000020
21void fpga_console_init(void);
22
Oliver Swedeb51da812019-12-03 14:08:21 +000023void plat_fpga_gic_init(void);
24void fpga_pwr_gic_on_finish(void);
25void fpga_pwr_gic_off(void);
Javier Almansa Sobrinofc78c3c2020-05-13 14:09:58 +010026unsigned int plat_fpga_calc_core_pos(uint32_t mpid);
Andre Przywara210541b2020-08-24 18:34:50 +010027unsigned int fpga_get_nr_gic_cores(void);
Andre Przywara42ba7c92021-05-18 15:53:05 +010028uintptr_t fpga_get_redist_size(void);
Javier Almansa Sobrinofc78c3c2020-05-13 14:09:58 +010029
30#endif /* __ASSEMBLER__ */
Oliver Swedeb51da812019-12-03 14:08:21 +000031
Javier Almansa Sobrinofc78c3c2020-05-13 14:09:58 +010032#endif /* FPGA_PRIVATE_H */