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Haojian Zhuang5f281b32017-05-24 08:45:05 +08001/*
Haojian Zhuangb755da32018-01-25 16:10:14 +08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang5f281b32017-05-24 08:45:05 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl_common.h>
10#include <console.h>
11#include <debug.h>
12#include <dw_mmc.h>
13#include <emmc.h>
14#include <errno.h>
Haojian Zhuang5f281b32017-05-24 08:45:05 +080015#include <hi6220.h>
Haojian Zhuang5f281b32017-05-24 08:45:05 +080016#include <mmio.h>
Haojian Zhuang5f281b32017-05-24 08:45:05 +080017#include <platform.h>
18#include <platform_def.h>
Haojian Zhuang5f281b32017-05-24 08:45:05 +080019#include <string.h>
20#include <tbbr/tbbr_img_desc.h>
21
22#include "../../bl1/bl1_private.h"
23#include "hikey_def.h"
24#include "hikey_private.h"
25
26/*
27 * Declarations of linker defined symbols which will help us find the layout
28 * of trusted RAM
29 */
30extern unsigned long __COHERENT_RAM_START__;
31extern unsigned long __COHERENT_RAM_END__;
32
33/*
34 * The next 2 constants identify the extents of the coherent memory region.
35 * These addresses are used by the MMU setup code and therefore they must be
36 * page-aligned. It is the responsibility of the linker script to ensure that
37 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
38 * page-aligned addresses.
39 */
40#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
41#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
42
43/* Data structure which holds the extents of the trusted RAM for BL1 */
44static meminfo_t bl1_tzram_layout;
45
46enum {
47 BOOT_NORMAL = 0,
48 BOOT_USB_DOWNLOAD,
49 BOOT_UART_DOWNLOAD,
50};
51
52meminfo_t *bl1_plat_sec_mem_layout(void)
53{
54 return &bl1_tzram_layout;
55}
56
Victor Chong2d9a42d2017-08-17 15:21:10 +090057/*******************************************************************************
58 * Function that takes a memory layout into which BL2 has been loaded and
59 * populates a new memory layout for BL2 that ensures that BL1's data sections
60 * resident in secure RAM are not visible to BL2.
61 ******************************************************************************/
62void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
63 meminfo_t *bl2_mem_layout)
64{
65
66 assert(bl1_mem_layout != NULL);
67 assert(bl2_mem_layout != NULL);
68
69 /*
70 * Cannot remove BL1 RW data from the scope of memory visible to BL2
71 * like arm platforms because they overlap in hikey
72 */
73 bl2_mem_layout->total_base = BL2_BASE;
74 bl2_mem_layout->total_size = BL32_SRAM_LIMIT - BL2_BASE;
75
76 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
77}
Victor Chong2d9a42d2017-08-17 15:21:10 +090078
Haojian Zhuang5f281b32017-05-24 08:45:05 +080079/*
80 * Perform any BL1 specific platform actions.
81 */
82void bl1_early_platform_setup(void)
83{
Haojian Zhuang5f281b32017-05-24 08:45:05 +080084 /* Initialize the console to provide early debug support */
85 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
86
87 /* Allow BL1 to see the whole Trusted RAM */
88 bl1_tzram_layout.total_base = BL1_RW_BASE;
89 bl1_tzram_layout.total_size = BL1_RW_SIZE;
90
Haojian Zhuang5f281b32017-05-24 08:45:05 +080091 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
Victor Chong2d9a42d2017-08-17 15:21:10 +090092 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
Haojian Zhuang5f281b32017-05-24 08:45:05 +080093}
94
95/*
96 * Perform the very early platform specific architecture setup here. At the
97 * moment this only does basic initialization. Later architectural setup
98 * (bl1_arch_setup()) does not do anything platform specific.
99 */
100void bl1_plat_arch_setup(void)
101{
102 hikey_init_mmu_el3(bl1_tzram_layout.total_base,
103 bl1_tzram_layout.total_size,
104 BL1_RO_BASE,
105 BL1_RO_LIMIT,
106 BL1_COHERENT_RAM_BASE,
107 BL1_COHERENT_RAM_LIMIT);
108}
109
Haojian Zhuang5f281b32017-05-24 08:45:05 +0800110/*
111 * Function which will perform any remaining platform-specific setup that can
112 * occur after the MMU and data cache have been enabled.
113 */
114void bl1_platform_setup(void)
115{
116 dw_mmc_params_t params;
117
118 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
119 ((SRAM_BASE + SRAM_SIZE) >=
120 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE)));
121 hikey_sp804_init();
122 hikey_gpio_init();
123 hikey_pmussi_init();
124 hikey_hi6553_init();
125
Haojian Zhuange1be9042017-10-18 19:56:02 +0800126 hikey_rtc_init();
127
Haojian Zhuang5f281b32017-05-24 08:45:05 +0800128 hikey_mmc_pll_init();
129
130 memset(&params, 0, sizeof(dw_mmc_params_t));
131 params.reg_base = DWMMC0_BASE;
132 params.desc_base = HIKEY_BL1_MMC_DESC_BASE;
133 params.desc_size = 1 << 20;
134 params.clk_rate = 24 * 1000 * 1000;
135 params.bus_width = EMMC_BUS_WIDTH_8;
136 params.flags = EMMC_FLAG_CMD23;
137 dw_mmc_init(&params);
138
139 hikey_io_setup();
140}
141
142/*
143 * The following function checks if Firmware update is needed,
144 * by checking if TOC in FIP image is valid or not.
145 */
146unsigned int bl1_plat_get_next_image_id(void)
147{
148 int32_t boot_mode;
149 unsigned int ret;
150
151 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE);
152 switch (boot_mode) {
Haojian Zhuang5f281b32017-05-24 08:45:05 +0800153 case BOOT_USB_DOWNLOAD:
154 case BOOT_UART_DOWNLOAD:
155 ret = NS_BL1U_IMAGE_ID;
156 break;
157 default:
158 WARN("Invalid boot mode is found:%d\n", boot_mode);
159 panic();
160 }
161 return ret;
162}
163
164image_desc_t *bl1_plat_get_image_desc(unsigned int image_id)
165{
166 unsigned int index = 0;
167
168 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) {
169 if (bl1_tbbr_image_descs[index].image_id == image_id)
170 return &bl1_tbbr_image_descs[index];
171
172 index++;
173 }
174
175 return NULL;
176}
177
178void bl1_plat_set_ep_info(unsigned int image_id,
179 entry_point_info_t *ep_info)
180{
Haojian Zhuang24c83372018-03-02 14:25:41 +0800181 uint64_t data = 0;
Haojian Zhuang5f281b32017-05-24 08:45:05 +0800182
183 if (image_id == BL2_IMAGE_ID)
Haojian Zhuangb755da32018-01-25 16:10:14 +0800184 panic();
Haojian Zhuang5f281b32017-05-24 08:45:05 +0800185 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE);
186 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
187 do {
188 data |= 3 << 20;
189 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data));
190 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
191 } while ((data & (3 << 20)) != (3 << 20));
Haojian Zhuang24c83372018-03-02 14:25:41 +0800192 INFO("cpacr_el1:0x%lx\n", data);
Haojian Zhuang5f281b32017-05-24 08:45:05 +0800193
194 ep_info->args.arg0 = 0xffff & read_mpidr();
195 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
196 DISABLE_ALL_EXCEPTIONS);
197}