blob: 92c83b06ec32bee0ce71a4e90d145cf5a1f1498c [file] [log] [blame]
Andre Przywara13815472018-06-01 02:01:39 +01001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/debug.h>
8#include <lib/mmio.h>
9
Andre Przywara13815472018-06-01 02:01:39 +010010#include <sunxi_mmap.h>
Andre Przywara456208a2018-10-14 12:02:02 +010011#include <sunxi_private.h>
Andre Przywara13815472018-06-01 02:01:39 +010012
13#ifdef SUNXI_SPC_BASE
14#define SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x4)
15#define SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x8)
16#define SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc)
17#endif
18
19#define R_PRCM_SEC_SWITCH_REG 0x1d0
20#define DMA_SEC_REG 0x20
21
22/*
23 * Setup the peripherals to be accessible by non-secure world.
24 * This will not work for the Secure Peripherals Controller (SPC) unless
25 * a fuse it burnt (seems to be an erratum), but we do it nevertheless,
26 * to allow booting on boards using secure boot.
27 */
28void sunxi_security_setup(void)
29{
Andre Przywarabd60b022018-06-22 00:28:31 +010030#ifdef SUNXI_SPC_BASE
Andre Przywara13815472018-06-01 02:01:39 +010031 int i;
32
Andre Przywara13815472018-06-01 02:01:39 +010033 INFO("Configuring SPC Controller\n");
34 /* SPC setup: set all devices to non-secure */
35 for (i = 0; i < 6; i++)
36 mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
37#endif
38
39 /* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */
40 mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);
41
Samuel Holland62d401a2019-12-29 16:12:12 -060042 /* Set R_PRCM bus clocks to non-secure */
43 mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x1);
Andre Przywara13815472018-06-01 02:01:39 +010044
45 /* Set all DMA channels (16 max.) to non-secure */
46 mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff);
47}