blob: e25b0e6d491c0898a022112f63a85e2876922930 [file] [log] [blame]
Jacky Bai64130a32019-07-18 13:43:17 +08001/*
2 * Copyright (c) 2019, NXP. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef IMX_RDC_H
8#define IMX_RDC_H
9
10#include <lib/utils_def.h>
11
12#include <platform_def.h>
13
14#define MDAn(x) (IMX_RDC_BASE + 0x200 + (x) * 4)
15#define PDAPn(x) (IMX_RDC_BASE + 0x400 + (x) * 4)
Jacky Baia5a8bae2019-11-29 10:25:42 +080016#define MRSAn(x) (IMX_RDC_BASE + 0x800 + (x) * 0x10)
17#define MREAn(x) (IMX_RDC_BASE + 0x804 + (x) * 0x10)
18#define MRCn(x) (IMX_RDC_BASE + 0x808 + (x) * 0x10)
Jacky Bai64130a32019-07-18 13:43:17 +080019
20#define LCK BIT(31)
21#define SREQ BIT(30)
22#define ENA BIT(30)
23
24#define DID0 U(0x0)
25#define DID1 U(0x1)
26#define DID2 U(0x2)
27#define DID3 U(0x3)
28
29#define D3R BIT(7)
30#define D3W BIT(6)
31#define D2R BIT(5)
32#define D2W BIT(4)
33#define D1R BIT(3)
34#define D1W BIT(2)
35#define D0R BIT(1)
36#define D0W BIT(0)
37
38union rdc_setting {
39 uint32_t rdc_mda; /* Master Domain Assignment */
40 uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */
41 uint32_t rdc_mem_region[3]; /* Memory Region Access Control */
42};
43
44enum rdc_type {
45 RDC_INVALID,
46 RDC_MDA,
47 RDC_PDAP,
48 RDC_MEM_REGION,
49};
50
51struct imx_rdc_cfg {
52 enum rdc_type type; /* config type Master, Peripheral or Memory region */
53 int index;
54 union rdc_setting setting;
55};
56
57#define RDC_MDAn(i, mda) \
58 {RDC_MDA, (i), .setting.rdc_mda = (mda), }
59#define RDC_PDAPn(i, pdap) \
60 {RDC_PDAP, (i), .setting.rdc_pdap = (pdap), }
61
62#define RDC_MEM_REGIONn(i, msa, mea, mrc) \
63 { RDC_MEM_REGION, (i), \
64 .setting.rdc_mem_region[0] = (msa), \
65 .setting.rdc_mem_region[1] = (mea), \
66 .setting.rdc_mem_region[2] = (mrc), \
67 }
68
69void imx_rdc_init(const struct imx_rdc_cfg *cfg);
70
71#endif /* IMX_RDC_H */
72