blob: 46a9f24c22d09c629012a828a97b4ba6c6521a62 [file] [log] [blame]
Dan Handleyed6ff952014-05-14 17:44:19 +01001/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_DEF_H__
32#define __PLATFORM_DEF_H__
33
34#include <arch.h>
35
36
37/*******************************************************************************
38 * Platform binary types for linking
39 ******************************************************************************/
40#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
41#define PLATFORM_LINKER_ARCH aarch64
42
43/*******************************************************************************
44 * Generic platform constants
45 ******************************************************************************/
46
47/* Size of cacheable stacks */
48#define PLATFORM_STACK_SIZE 0x800
49
50/* Size of coherent stacks for debug and release builds */
51#if DEBUG
52#define PCPU_DV_MEM_STACK_SIZE 0x400
53#else
54#define PCPU_DV_MEM_STACK_SIZE 0x300
55#endif
56
57#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
58
59/* Trusted Boot Firmware BL2 */
60#define BL2_IMAGE_NAME "bl2.bin"
61
62/* EL3 Runtime Firmware BL31 */
63#define BL31_IMAGE_NAME "bl31.bin"
64
65/* Secure Payload BL32 (Trusted OS) */
66#define BL32_IMAGE_NAME "bl32.bin"
67
68/* Non-Trusted Firmware BL33 */
69#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
70
71#define PLATFORM_CACHE_LINE_SIZE 64
72#define PLATFORM_CLUSTER_COUNT 2ull
73#define PLATFORM_CLUSTER0_CORE_COUNT 4
74#define PLATFORM_CLUSTER1_CORE_COUNT 4
75#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
76 PLATFORM_CLUSTER0_CORE_COUNT)
77#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
78#define PRIMARY_CPU 0x0
79#define MAX_IO_DEVICES 3
80#define MAX_IO_HANDLES 4
81
82/*******************************************************************************
83 * Platform memory map related constants
84 ******************************************************************************/
85#define TZROM_BASE 0x00000000
86#define TZROM_SIZE 0x04000000
87
88#define TZRAM_BASE 0x04000000
89#define TZRAM_SIZE 0x40000
90
91/* Location of trusted dram on the base fvp */
92#define TZDRAM_BASE 0x06000000
93#define TZDRAM_SIZE 0x02000000
94
95/*******************************************************************************
96 * BL1 specific defines.
97 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
98 * addresses.
99 ******************************************************************************/
100#define BL1_RO_BASE TZROM_BASE
101#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
102#define BL1_RW_BASE TZRAM_BASE
103#define BL1_RW_LIMIT BL31_BASE
104
105/*******************************************************************************
106 * BL2 specific defines.
107 ******************************************************************************/
108#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000)
109#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE)
110
111/*******************************************************************************
112 * BL31 specific defines.
113 ******************************************************************************/
114#define BL31_BASE (TZRAM_BASE + 0x6000)
115#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
116#define BL31_LIMIT BL32_BASE
117#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
118#define BL31_LIMIT BL2_BASE
119#endif
120
121/*******************************************************************************
122 * BL32 specific defines.
123 ******************************************************************************/
124/*
125 * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
126 */
127#define TSP_IN_TZRAM 0
128#define TSP_IN_TZDRAM 1
129
130#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
131# define TSP_SEC_MEM_BASE TZRAM_BASE
132# define TSP_SEC_MEM_SIZE TZRAM_SIZE
133# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000)
134# define BL32_LIMIT BL2_BASE
135#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
136# define TSP_SEC_MEM_BASE TZDRAM_BASE
137# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
138# define BL32_BASE (TZDRAM_BASE + 0x2000)
139# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
140#else
141# error "Unsupported TSP_RAM_LOCATION_ID value"
142#endif
143
144/*******************************************************************************
145 * Platform specific page table and MMU setup constants
146 ******************************************************************************/
147#define ADDR_SPACE_SIZE (1ull << 32)
148#define MAX_XLAT_TABLES 3
149#define MAX_MMAP_REGIONS 16
150
151/*******************************************************************************
152 * ID of the secure physical generic timer interrupt.
153 ******************************************************************************/
154#define IRQ_SEC_PHY_TIMER 29
155
156/*******************************************************************************
157 * CCI-400 related constants
158 ******************************************************************************/
159#define CCI400_BASE 0x2c090000
160#define CCI400_SL_IFACE_CLUSTER0 3
161#define CCI400_SL_IFACE_CLUSTER1 4
162#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
163 CCI400_SL_IFACE_CLUSTER1 : \
164 CCI400_SL_IFACE_CLUSTER0)
165
166
167/*******************************************************************************
168 * Declarations and constants to access the mailboxes safely. Each mailbox is
169 * aligned on the biggest cache line size in the platform. This is known only
170 * to the platform as it might have a combination of integrated and external
171 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
172 * line at any cache level. They could belong to different cpus/clusters &
173 * get written while being protected by different locks causing corruption of
174 * a valid mailbox address.
175 ******************************************************************************/
176#define CACHE_WRITEBACK_SHIFT 6
177#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
178
179
180#endif /* __PLATFORM_DEF_H__ */