Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 32 | #include <asm_macros.S> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <context.h> |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 34 | #include <interrupt_mgmt.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 35 | #include <platform_def.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 36 | #include <runtime_svc.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | |
| 38 | .globl runtime_exceptions |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 39 | .globl el3_exit |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 41 | /* ----------------------------------------------------- |
| 42 | * Handle SMC exceptions seperately from other sync. |
| 43 | * exceptions. |
| 44 | * ----------------------------------------------------- |
| 45 | */ |
| 46 | .macro handle_sync_exception |
| 47 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 48 | mrs x30, esr_el3 |
| 49 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 50 | |
| 51 | cmp x30, #EC_AARCH32_SMC |
| 52 | b.eq smc_handler32 |
| 53 | |
| 54 | cmp x30, #EC_AARCH64_SMC |
| 55 | b.eq smc_handler64 |
| 56 | |
| 57 | /* ----------------------------------------------------- |
| 58 | * The following code handles any synchronous exception |
| 59 | * that is not an SMC. |
| 60 | * ----------------------------------------------------- |
| 61 | */ |
| 62 | |
| 63 | bl dump_state_and_die |
| 64 | .endm |
| 65 | |
| 66 | |
| 67 | /* ----------------------------------------------------- |
| 68 | * This macro handles FIQ or IRQ interrupts i.e. EL3, |
| 69 | * S-EL1 and NS interrupts. |
| 70 | * ----------------------------------------------------- |
| 71 | */ |
| 72 | .macro handle_interrupt_exception label |
| 73 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 74 | bl save_gp_registers |
| 75 | |
| 76 | /* Switch to the runtime stack i.e. SP_EL0 */ |
| 77 | ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 78 | mov x20, sp |
| 79 | msr spsel, #0 |
| 80 | mov sp, x2 |
| 81 | |
| 82 | /* |
| 83 | * Find out whether this is a valid interrupt type. If the |
| 84 | * interrupt controller reports a spurious interrupt then |
| 85 | * return to where we came from. |
| 86 | */ |
Dan Handley | 701fea7 | 2014-05-27 16:17:21 +0100 | [diff] [blame] | 87 | bl plat_ic_get_pending_interrupt_type |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 88 | cmp x0, #INTR_TYPE_INVAL |
| 89 | b.eq interrupt_exit_\label |
| 90 | |
| 91 | /* |
| 92 | * Get the registered handler for this interrupt type. A |
| 93 | * NULL return value implies that an interrupt was generated |
| 94 | * for which there is no handler registered or the interrupt |
| 95 | * was routed incorrectly. This is a problem of the framework |
| 96 | * so report it as an error. |
| 97 | */ |
| 98 | bl get_interrupt_type_handler |
| 99 | cbz x0, interrupt_error_\label |
| 100 | mov x21, x0 |
| 101 | |
| 102 | mov x0, #INTR_ID_UNAVAILABLE |
| 103 | #if IMF_READ_INTERRUPT_ID |
| 104 | /* |
| 105 | * Read the id of the highest priority pending interrupt. If |
| 106 | * no interrupt is asserted then return to where we came from. |
| 107 | */ |
Dan Handley | 701fea7 | 2014-05-27 16:17:21 +0100 | [diff] [blame] | 108 | bl plat_ic_get_pending_interrupt_id |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 109 | cmp x0, #INTR_ID_UNAVAILABLE |
| 110 | b.eq interrupt_exit_\label |
| 111 | #endif |
| 112 | |
| 113 | /* |
| 114 | * Save the EL3 system registers needed to return from |
| 115 | * this exception. |
| 116 | */ |
| 117 | mrs x3, spsr_el3 |
| 118 | mrs x4, elr_el3 |
| 119 | stp x3, x4, [x20, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 120 | |
| 121 | /* Set the current security state in the 'flags' parameter */ |
| 122 | mrs x2, scr_el3 |
| 123 | ubfx x1, x2, #0, #1 |
| 124 | |
| 125 | /* Restore the reference to the 'handle' i.e. SP_EL3 */ |
| 126 | mov x2, x20 |
| 127 | |
| 128 | /* Call the interrupt type handler */ |
| 129 | blr x21 |
| 130 | |
| 131 | interrupt_exit_\label: |
| 132 | /* Return from exception, possibly in a different security state */ |
| 133 | b el3_exit |
| 134 | |
| 135 | /* |
| 136 | * This label signifies a problem with the interrupt management |
| 137 | * framework where it is not safe to go back to the instruction |
| 138 | * where the interrupt was generated. |
| 139 | */ |
| 140 | interrupt_error_\label: |
| 141 | bl dump_intr_state_and_die |
| 142 | .endm |
| 143 | |
| 144 | |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 145 | .macro save_x18_to_x29_sp_el0 |
| 146 | stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] |
| 147 | stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] |
| 148 | stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] |
| 149 | stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] |
| 150 | stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] |
| 151 | stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] |
| 152 | mrs x18, sp_el0 |
| 153 | str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] |
| 154 | .endm |
| 155 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 156 | .section .vectors, "ax"; .align 11 |
| 157 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 158 | .align 7 |
| 159 | runtime_exceptions: |
| 160 | /* ----------------------------------------------------- |
| 161 | * Current EL with _sp_el0 : 0x0 - 0x180 |
| 162 | * ----------------------------------------------------- |
| 163 | */ |
| 164 | sync_exception_sp_el0: |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 165 | /* ----------------------------------------------------- |
| 166 | * We don't expect any synchronous exceptions from EL3 |
| 167 | * ----------------------------------------------------- |
| 168 | */ |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 169 | bl dump_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 170 | check_vector_size sync_exception_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 171 | |
| 172 | .align 7 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 173 | /* ----------------------------------------------------- |
| 174 | * EL3 code is non-reentrant. Any asynchronous exception |
| 175 | * is a serious error. Loop infinitely. |
| 176 | * ----------------------------------------------------- |
| 177 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 178 | irq_sp_el0: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 179 | bl dump_intr_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 180 | check_vector_size irq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 181 | |
| 182 | .align 7 |
| 183 | fiq_sp_el0: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 184 | bl dump_intr_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 185 | check_vector_size fiq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 186 | |
| 187 | .align 7 |
| 188 | serror_sp_el0: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 189 | bl dump_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 190 | check_vector_size serror_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 191 | |
| 192 | /* ----------------------------------------------------- |
| 193 | * Current EL with SPx: 0x200 - 0x380 |
| 194 | * ----------------------------------------------------- |
| 195 | */ |
| 196 | .align 7 |
| 197 | sync_exception_sp_elx: |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 198 | /* ----------------------------------------------------- |
| 199 | * This exception will trigger if anything went wrong |
| 200 | * during a previous exception entry or exit or while |
| 201 | * handling an earlier unexpected synchronous exception. |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 202 | * There is a high probability that SP_EL3 is corrupted. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 203 | * ----------------------------------------------------- |
| 204 | */ |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 205 | bl dump_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 206 | check_vector_size sync_exception_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 207 | |
| 208 | .align 7 |
| 209 | irq_sp_elx: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 210 | bl dump_intr_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 211 | check_vector_size irq_sp_elx |
| 212 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 213 | .align 7 |
| 214 | fiq_sp_elx: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 215 | bl dump_intr_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 216 | check_vector_size fiq_sp_elx |
| 217 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 218 | .align 7 |
| 219 | serror_sp_elx: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 220 | bl dump_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 221 | check_vector_size serror_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 222 | |
| 223 | /* ----------------------------------------------------- |
| 224 | * Lower EL using AArch64 : 0x400 - 0x580 |
| 225 | * ----------------------------------------------------- |
| 226 | */ |
| 227 | .align 7 |
| 228 | sync_exception_aarch64: |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 229 | /* ----------------------------------------------------- |
| 230 | * This exception vector will be the entry point for |
| 231 | * SMCs and traps that are unhandled at lower ELs most |
| 232 | * commonly. SP_EL3 should point to a valid cpu context |
| 233 | * where the general purpose and system register state |
| 234 | * can be saved. |
| 235 | * ----------------------------------------------------- |
| 236 | */ |
| 237 | handle_sync_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 238 | check_vector_size sync_exception_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 239 | |
| 240 | .align 7 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 241 | /* ----------------------------------------------------- |
| 242 | * Asynchronous exceptions from lower ELs are not |
| 243 | * currently supported. Report their occurrence. |
| 244 | * ----------------------------------------------------- |
| 245 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 246 | irq_aarch64: |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 247 | handle_interrupt_exception irq_aarch64 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 248 | check_vector_size irq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 249 | |
| 250 | .align 7 |
| 251 | fiq_aarch64: |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 252 | handle_interrupt_exception fiq_aarch64 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 253 | check_vector_size fiq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 254 | |
| 255 | .align 7 |
| 256 | serror_aarch64: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 257 | bl dump_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 258 | check_vector_size serror_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 259 | |
| 260 | /* ----------------------------------------------------- |
| 261 | * Lower EL using AArch32 : 0x600 - 0x780 |
| 262 | * ----------------------------------------------------- |
| 263 | */ |
| 264 | .align 7 |
| 265 | sync_exception_aarch32: |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 266 | /* ----------------------------------------------------- |
| 267 | * This exception vector will be the entry point for |
| 268 | * SMCs and traps that are unhandled at lower ELs most |
| 269 | * commonly. SP_EL3 should point to a valid cpu context |
| 270 | * where the general purpose and system register state |
| 271 | * can be saved. |
| 272 | * ----------------------------------------------------- |
| 273 | */ |
| 274 | handle_sync_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 275 | check_vector_size sync_exception_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 276 | |
| 277 | .align 7 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 278 | /* ----------------------------------------------------- |
| 279 | * Asynchronous exceptions from lower ELs are not |
| 280 | * currently supported. Report their occurrence. |
| 281 | * ----------------------------------------------------- |
| 282 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 283 | irq_aarch32: |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 284 | handle_interrupt_exception irq_aarch32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 285 | check_vector_size irq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 286 | |
| 287 | .align 7 |
| 288 | fiq_aarch32: |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 289 | handle_interrupt_exception fiq_aarch32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 290 | check_vector_size fiq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 291 | |
| 292 | .align 7 |
| 293 | serror_aarch32: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 294 | bl dump_state_and_die |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 295 | check_vector_size serror_aarch32 |
| 296 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 297 | .align 7 |
| 298 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 299 | /* ----------------------------------------------------- |
| 300 | * The following code handles secure monitor calls. |
| 301 | * Depending upon the execution state from where the SMC |
| 302 | * has been invoked, it frees some general purpose |
| 303 | * registers to perform the remaining tasks. They |
| 304 | * involve finding the runtime service handler that is |
| 305 | * the target of the SMC & switching to runtime stacks |
| 306 | * (SP_EL0) before calling the handler. |
| 307 | * |
| 308 | * Note that x30 has been explicitly saved and can be |
| 309 | * used here |
| 310 | * ----------------------------------------------------- |
| 311 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 312 | func smc_handler |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 313 | smc_handler32: |
| 314 | /* Check whether aarch32 issued an SMC64 */ |
| 315 | tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited |
| 316 | |
| 317 | /* ----------------------------------------------------- |
| 318 | * Since we're are coming from aarch32, x8-x18 need to |
| 319 | * be saved as per SMC32 calling convention. If a lower |
| 320 | * EL in aarch64 is making an SMC32 call then it must |
| 321 | * have saved x8-x17 already therein. |
| 322 | * ----------------------------------------------------- |
| 323 | */ |
| 324 | stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] |
| 325 | stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] |
| 326 | stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] |
| 327 | stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] |
| 328 | stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] |
| 329 | |
| 330 | /* x4-x7, x18, sp_el0 are saved below */ |
| 331 | |
| 332 | smc_handler64: |
| 333 | /* ----------------------------------------------------- |
| 334 | * Populate the parameters for the SMC handler. We |
| 335 | * already have x0-x4 in place. x5 will point to a |
| 336 | * cookie (not used now). x6 will point to the context |
| 337 | * structure (SP_EL3) and x7 will contain flags we need |
| 338 | * to pass to the handler Hence save x5-x7. Note that x4 |
| 339 | * only needs to be preserved for AArch32 callers but we |
| 340 | * do it for AArch64 callers as well for convenience |
| 341 | * ----------------------------------------------------- |
| 342 | */ |
| 343 | stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] |
| 344 | stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] |
| 345 | |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 346 | /* Save rest of the gpregs and sp_el0*/ |
| 347 | save_x18_to_x29_sp_el0 |
| 348 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 349 | mov x5, xzr |
| 350 | mov x6, sp |
| 351 | |
| 352 | /* Get the unique owning entity number */ |
| 353 | ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH |
| 354 | ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH |
| 355 | orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH |
| 356 | |
| 357 | adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) |
| 358 | |
| 359 | /* Load descriptor index from array of indices */ |
| 360 | adr x14, rt_svc_descs_indices |
| 361 | ldrb w15, [x14, x16] |
| 362 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 363 | /* ----------------------------------------------------- |
| 364 | * Restore the saved C runtime stack value which will |
| 365 | * become the new SP_EL0 i.e. EL3 runtime stack. It was |
| 366 | * saved in the 'cpu_context' structure prior to the last |
| 367 | * ERET from EL3. |
| 368 | * ----------------------------------------------------- |
| 369 | */ |
| 370 | ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 371 | |
| 372 | /* |
| 373 | * Any index greater than 127 is invalid. Check bit 7 for |
| 374 | * a valid index |
| 375 | */ |
| 376 | tbnz w15, 7, smc_unknown |
| 377 | |
| 378 | /* Switch to SP_EL0 */ |
| 379 | msr spsel, #0 |
| 380 | |
| 381 | /* ----------------------------------------------------- |
| 382 | * Get the descriptor using the index |
| 383 | * x11 = (base + off), x15 = index |
| 384 | * |
| 385 | * handler = (base + off) + (index << log2(size)) |
| 386 | * ----------------------------------------------------- |
| 387 | */ |
| 388 | lsl w10, w15, #RT_SVC_SIZE_LOG2 |
| 389 | ldr x15, [x11, w10, uxtw] |
| 390 | |
| 391 | /* ----------------------------------------------------- |
| 392 | * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there |
| 393 | * is a world switch during SMC handling. |
| 394 | * TODO: Revisit if all system registers can be saved |
| 395 | * later. |
| 396 | * ----------------------------------------------------- |
| 397 | */ |
| 398 | mrs x16, spsr_el3 |
| 399 | mrs x17, elr_el3 |
| 400 | mrs x18, scr_el3 |
| 401 | stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 402 | stp x18, xzr, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] |
| 403 | |
| 404 | /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ |
| 405 | bfi x7, x18, #0, #1 |
| 406 | |
| 407 | mov sp, x12 |
| 408 | |
| 409 | /* ----------------------------------------------------- |
| 410 | * Call the Secure Monitor Call handler and then drop |
| 411 | * directly into el3_exit() which will program any |
| 412 | * remaining architectural state prior to issuing the |
| 413 | * ERET to the desired lower EL. |
| 414 | * ----------------------------------------------------- |
| 415 | */ |
| 416 | #if DEBUG |
| 417 | cbz x15, rt_svc_fw_critical_error |
| 418 | #endif |
| 419 | blr x15 |
| 420 | |
| 421 | /* ----------------------------------------------------- |
| 422 | * This routine assumes that the SP_EL3 is pointing to |
| 423 | * a valid context structure from where the gp regs and |
| 424 | * other special registers can be retrieved. |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 425 | * |
| 426 | * Keep it in the same section as smc_handler as this |
| 427 | * function uses a fall-through to el3_exit |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 428 | * ----------------------------------------------------- |
| 429 | */ |
| 430 | el3_exit: ; .type el3_exit, %function |
| 431 | /* ----------------------------------------------------- |
| 432 | * Save the current SP_EL0 i.e. the EL3 runtime stack |
| 433 | * which will be used for handling the next SMC. Then |
| 434 | * switch to SP_EL3 |
| 435 | * ----------------------------------------------------- |
| 436 | */ |
| 437 | mov x17, sp |
| 438 | msr spsel, #1 |
| 439 | str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 440 | |
| 441 | /* ----------------------------------------------------- |
| 442 | * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET |
| 443 | * ----------------------------------------------------- |
| 444 | */ |
| 445 | ldp x18, xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] |
| 446 | ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 447 | msr scr_el3, x18 |
| 448 | msr spsr_el3, x16 |
| 449 | msr elr_el3, x17 |
| 450 | |
| 451 | /* Restore saved general purpose registers and return */ |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 452 | b restore_gp_registers_eret |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 453 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 454 | smc_unknown: |
| 455 | /* |
| 456 | * Here we restore x4-x18 regardless of where we came from. AArch32 |
| 457 | * callers will find the registers contents unchanged, but AArch64 |
| 458 | * callers will find the registers modified (with stale earlier NS |
| 459 | * content). Either way, we aren't leaking any secure information |
| 460 | * through them |
| 461 | */ |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 462 | mov w0, #SMC_UNK |
| 463 | b restore_gp_registers_callee_eret |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 464 | |
| 465 | smc_prohibited: |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 466 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 467 | mov w0, #SMC_UNK |
| 468 | eret |
| 469 | |
| 470 | rt_svc_fw_critical_error: |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 471 | msr spsel, #1 /* Switch to SP_ELx */ |
| 472 | bl dump_state_and_die |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 473 | |
| 474 | /* ----------------------------------------------------- |
| 475 | * The following functions are used to saved and restore |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 476 | * all the general pupose registers. Ideally we would |
| 477 | * only save and restore the callee saved registers when |
| 478 | * a world switch occurs but that type of implementation |
| 479 | * is more complex. So currently we will always save and |
| 480 | * restore these registers on entry and exit of EL3. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 481 | * These are not macros to ensure their invocation fits |
| 482 | * within the 32 instructions per exception vector. |
| 483 | * ----------------------------------------------------- |
| 484 | */ |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 485 | func save_gp_registers |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 486 | stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] |
| 487 | stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] |
| 488 | stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] |
| 489 | stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] |
| 490 | stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] |
| 491 | stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] |
| 492 | stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] |
| 493 | stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] |
| 494 | stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 495 | save_x18_to_x29_sp_el0 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 496 | ret |
| 497 | |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 498 | func restore_gp_registers_eret |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 499 | ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] |
| 500 | ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] |
| 501 | |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 502 | restore_gp_registers_callee_eret: |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 503 | ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] |
| 504 | ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] |
| 505 | ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] |
| 506 | ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] |
| 507 | ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] |
| 508 | ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 509 | ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] |
| 510 | ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] |
| 511 | ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] |
| 512 | ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] |
| 513 | ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] |
| 514 | ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 515 | ldp x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 516 | msr sp_el0, x17 |
| 517 | ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] |
| 518 | eret |