Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 31 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 32 | #include <bl_common.h> |
| 33 | #include <bl32.h> |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 34 | #include <debug.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 35 | #include <platform.h> |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 36 | #include <spinlock.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 37 | #include <stdio.h> |
| 38 | #include <tsp.h> |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 39 | |
| 40 | /******************************************************************************* |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame] | 41 | * Declarations of linker defined symbols which will help us find the layout |
| 42 | * of trusted SRAM |
| 43 | ******************************************************************************/ |
| 44 | extern unsigned long __RO_START__; |
| 45 | extern unsigned long __COHERENT_RAM_END__; |
| 46 | |
| 47 | /******************************************************************************* |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 48 | * Lock to control access to the console |
| 49 | ******************************************************************************/ |
| 50 | spinlock_t console_lock; |
| 51 | |
| 52 | /******************************************************************************* |
| 53 | * Per cpu data structure to populate parameters for an SMC in C code and use |
| 54 | * a pointer to this structure in assembler code to populate x0-x7 |
| 55 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 56 | static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 57 | |
| 58 | /******************************************************************************* |
| 59 | * Per cpu data structure to keep track of TSP activity |
| 60 | ******************************************************************************/ |
Achin Gupta | 7671789 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 61 | work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 62 | |
| 63 | /******************************************************************************* |
| 64 | * Single reference to the various entry points exported by the test secure |
| 65 | * payload. A single copy should suffice for all cpus as they are not expected |
| 66 | * to change. |
| 67 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 68 | static const entry_info_t tsp_entry_info = { |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 69 | tsp_fast_smc_entry, |
| 70 | tsp_cpu_on_entry, |
| 71 | tsp_cpu_off_entry, |
| 72 | tsp_cpu_resume_entry, |
| 73 | tsp_cpu_suspend_entry, |
Achin Gupta | 7671789 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 74 | tsp_fiq_entry, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 75 | }; |
| 76 | |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame] | 77 | |
| 78 | /******************************************************************************* |
| 79 | * The BL32 memory footprint starts with an RO sections and ends |
| 80 | * with a section for coherent RAM. Use it to find the memory size |
| 81 | ******************************************************************************/ |
| 82 | #define BL32_TOTAL_BASE (unsigned long)(&__RO_START__) |
| 83 | |
| 84 | #define BL32_TOTAL_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
| 85 | |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 86 | static tsp_args_t *set_smc_args(uint64_t arg0, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 87 | uint64_t arg1, |
| 88 | uint64_t arg2, |
| 89 | uint64_t arg3, |
| 90 | uint64_t arg4, |
| 91 | uint64_t arg5, |
| 92 | uint64_t arg6, |
| 93 | uint64_t arg7) |
| 94 | { |
| 95 | uint64_t mpidr = read_mpidr(); |
| 96 | uint32_t linear_id; |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 97 | tsp_args_t *pcpu_smc_args; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 98 | |
| 99 | /* |
| 100 | * Return to Secure Monitor by raising an SMC. The results of the |
| 101 | * service are passed as an arguments to the SMC |
| 102 | */ |
| 103 | linear_id = platform_get_core_pos(mpidr); |
| 104 | pcpu_smc_args = &tsp_smc_args[linear_id]; |
| 105 | write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); |
| 106 | write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); |
| 107 | write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); |
| 108 | write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); |
| 109 | write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); |
| 110 | write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); |
| 111 | write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); |
| 112 | write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); |
| 113 | |
| 114 | return pcpu_smc_args; |
| 115 | } |
| 116 | |
| 117 | /******************************************************************************* |
| 118 | * TSP main entry point where it gets the opportunity to initialize its secure |
| 119 | * state/applications. Once the state is initialized, it must return to the |
| 120 | * SPD with a pointer to the 'tsp_entry_info' structure. |
| 121 | ******************************************************************************/ |
| 122 | uint64_t tsp_main(void) |
| 123 | { |
| 124 | uint64_t mpidr = read_mpidr(); |
| 125 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 126 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 127 | /* Initialize the platform */ |
| 128 | bl32_platform_setup(); |
| 129 | |
| 130 | /* Initialize secure/applications state here */ |
| 131 | |
| 132 | /* Update this cpu's statistics */ |
| 133 | tsp_stats[linear_id].smc_count++; |
| 134 | tsp_stats[linear_id].eret_count++; |
| 135 | tsp_stats[linear_id].cpu_on_count++; |
| 136 | |
| 137 | spin_lock(&console_lock); |
Jon Medhurst | ecf0a71 | 2014-02-17 12:18:24 +0000 | [diff] [blame] | 138 | printf("TSP %s\n\r", build_message); |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame] | 139 | INFO("Total memory base : 0x%x\n", (unsigned long)BL32_TOTAL_BASE); |
| 140 | INFO("Total memory size : 0x%x bytes\n", |
| 141 | (unsigned long)(BL32_TOTAL_LIMIT - BL32_TOTAL_BASE)); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 142 | INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, |
| 143 | tsp_stats[linear_id].smc_count, |
| 144 | tsp_stats[linear_id].eret_count, |
| 145 | tsp_stats[linear_id].cpu_on_count); |
| 146 | spin_unlock(&console_lock); |
| 147 | |
| 148 | /* |
| 149 | * TODO: There is a massive assumption that the SPD and SP can see each |
| 150 | * other's memory without issues so it is safe to pass pointers to |
| 151 | * internal memory. Replace this with a shared communication buffer. |
| 152 | */ |
| 153 | return (uint64_t) &tsp_entry_info; |
| 154 | } |
| 155 | |
| 156 | /******************************************************************************* |
| 157 | * This function performs any remaining book keeping in the test secure payload |
| 158 | * after this cpu's architectural state has been setup in response to an earlier |
| 159 | * psci cpu_on request. |
| 160 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 161 | tsp_args_t *tsp_cpu_on_main(void) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 162 | { |
| 163 | uint64_t mpidr = read_mpidr(); |
| 164 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 165 | |
| 166 | /* Update this cpu's statistics */ |
| 167 | tsp_stats[linear_id].smc_count++; |
| 168 | tsp_stats[linear_id].eret_count++; |
| 169 | tsp_stats[linear_id].cpu_on_count++; |
| 170 | |
| 171 | spin_lock(&console_lock); |
| 172 | printf("SP: cpu 0x%x turned on\n\r", mpidr); |
| 173 | INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, |
| 174 | tsp_stats[linear_id].smc_count, |
| 175 | tsp_stats[linear_id].eret_count, |
| 176 | tsp_stats[linear_id].cpu_on_count); |
| 177 | spin_unlock(&console_lock); |
| 178 | |
| 179 | /* Indicate to the SPD that we have completed turned ourselves on */ |
| 180 | return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); |
| 181 | } |
| 182 | |
| 183 | /******************************************************************************* |
| 184 | * This function performs any remaining book keeping in the test secure payload |
| 185 | * before this cpu is turned off in response to a psci cpu_off request. |
| 186 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 187 | tsp_args_t *tsp_cpu_off_main(uint64_t arg0, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 188 | uint64_t arg1, |
| 189 | uint64_t arg2, |
| 190 | uint64_t arg3, |
| 191 | uint64_t arg4, |
| 192 | uint64_t arg5, |
| 193 | uint64_t arg6, |
| 194 | uint64_t arg7) |
| 195 | { |
| 196 | uint64_t mpidr = read_mpidr(); |
| 197 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 198 | |
| 199 | /* Update this cpu's statistics */ |
| 200 | tsp_stats[linear_id].smc_count++; |
| 201 | tsp_stats[linear_id].eret_count++; |
| 202 | tsp_stats[linear_id].cpu_off_count++; |
| 203 | |
| 204 | spin_lock(&console_lock); |
| 205 | printf("SP: cpu 0x%x off request\n\r", mpidr); |
| 206 | INFO("cpu 0x%x: %d smcs, %d erets %d cpu off requests\n", mpidr, |
| 207 | tsp_stats[linear_id].smc_count, |
| 208 | tsp_stats[linear_id].eret_count, |
| 209 | tsp_stats[linear_id].cpu_off_count); |
| 210 | spin_unlock(&console_lock); |
| 211 | |
| 212 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 213 | /* Indicate to the SPD that we have completed this request */ |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 214 | return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); |
| 215 | } |
| 216 | |
| 217 | /******************************************************************************* |
| 218 | * This function performs any book keeping in the test secure payload before |
| 219 | * this cpu's architectural state is saved in response to an earlier psci |
| 220 | * cpu_suspend request. |
| 221 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 222 | tsp_args_t *tsp_cpu_suspend_main(uint64_t power_state, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 223 | uint64_t arg1, |
| 224 | uint64_t arg2, |
| 225 | uint64_t arg3, |
| 226 | uint64_t arg4, |
| 227 | uint64_t arg5, |
| 228 | uint64_t arg6, |
| 229 | uint64_t arg7) |
| 230 | { |
| 231 | uint64_t mpidr = read_mpidr(); |
| 232 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 233 | |
| 234 | /* Update this cpu's statistics */ |
| 235 | tsp_stats[linear_id].smc_count++; |
| 236 | tsp_stats[linear_id].eret_count++; |
| 237 | tsp_stats[linear_id].cpu_suspend_count++; |
| 238 | |
| 239 | spin_lock(&console_lock); |
| 240 | printf("SP: cpu 0x%x suspend request. power state: 0x%x\n\r", |
| 241 | mpidr, power_state); |
| 242 | INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, |
| 243 | tsp_stats[linear_id].smc_count, |
| 244 | tsp_stats[linear_id].eret_count, |
| 245 | tsp_stats[linear_id].cpu_suspend_count); |
| 246 | spin_unlock(&console_lock); |
| 247 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 248 | /* Indicate to the SPD that we have completed this request */ |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 249 | return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); |
| 250 | } |
| 251 | |
| 252 | /******************************************************************************* |
| 253 | * This function performs any book keeping in the test secure payload after this |
| 254 | * cpu's architectural state has been restored after wakeup from an earlier psci |
| 255 | * cpu_suspend request. |
| 256 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 257 | tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 258 | uint64_t arg1, |
| 259 | uint64_t arg2, |
| 260 | uint64_t arg3, |
| 261 | uint64_t arg4, |
| 262 | uint64_t arg5, |
| 263 | uint64_t arg6, |
| 264 | uint64_t arg7) |
| 265 | { |
| 266 | uint64_t mpidr = read_mpidr(); |
| 267 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 268 | |
| 269 | /* Update this cpu's statistics */ |
| 270 | tsp_stats[linear_id].smc_count++; |
| 271 | tsp_stats[linear_id].eret_count++; |
| 272 | tsp_stats[linear_id].cpu_resume_count++; |
| 273 | |
| 274 | spin_lock(&console_lock); |
| 275 | printf("SP: cpu 0x%x resumed. suspend level %d \n\r", |
| 276 | mpidr, suspend_level); |
| 277 | INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, |
| 278 | tsp_stats[linear_id].smc_count, |
| 279 | tsp_stats[linear_id].eret_count, |
| 280 | tsp_stats[linear_id].cpu_suspend_count); |
| 281 | spin_unlock(&console_lock); |
| 282 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 283 | /* Indicate to the SPD that we have completed this request */ |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 284 | return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); |
| 285 | } |
| 286 | |
| 287 | /******************************************************************************* |
| 288 | * TSP fast smc handler. The secure monitor jumps to this function by |
| 289 | * doing the ERET after populating X0-X7 registers. The arguments are received |
| 290 | * in the function arguments in order. Once the service is rendered, this |
| 291 | * function returns to Secure Monitor by raising SMC |
| 292 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 293 | tsp_args_t *tsp_fast_smc_handler(uint64_t func, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 294 | uint64_t arg1, |
| 295 | uint64_t arg2, |
| 296 | uint64_t arg3, |
| 297 | uint64_t arg4, |
| 298 | uint64_t arg5, |
| 299 | uint64_t arg6, |
| 300 | uint64_t arg7) |
| 301 | { |
Achin Gupta | 916a2c1 | 2014-02-09 23:11:46 +0000 | [diff] [blame] | 302 | uint64_t results[2]; |
| 303 | uint64_t service_args[2]; |
| 304 | uint64_t mpidr = read_mpidr(); |
| 305 | uint32_t linear_id = platform_get_core_pos(mpidr); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 306 | |
Achin Gupta | 916a2c1 | 2014-02-09 23:11:46 +0000 | [diff] [blame] | 307 | /* Update this cpu's statistics */ |
| 308 | tsp_stats[linear_id].smc_count++; |
| 309 | tsp_stats[linear_id].eret_count++; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 310 | |
Achin Gupta | 916a2c1 | 2014-02-09 23:11:46 +0000 | [diff] [blame] | 311 | printf("SP: cpu 0x%x received fast smc 0x%x\n", read_mpidr(), func); |
| 312 | INFO("cpu 0x%x: %d smcs, %d erets\n", mpidr, |
| 313 | tsp_stats[linear_id].smc_count, |
| 314 | tsp_stats[linear_id].eret_count); |
| 315 | |
| 316 | /* Render secure services and obtain results here */ |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 317 | |
| 318 | results[0] = arg1; |
| 319 | results[1] = arg2; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 320 | |
| 321 | /* |
| 322 | * Request a service back from dispatcher/secure monitor. This call |
| 323 | * return and thereafter resume exectuion |
| 324 | */ |
| 325 | tsp_get_magic(service_args); |
| 326 | |
| 327 | /* Determine the function to perform based on the function ID */ |
| 328 | switch (func) { |
| 329 | case TSP_FID_ADD: |
| 330 | results[0] += service_args[0]; |
| 331 | results[1] += service_args[1]; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 332 | break; |
| 333 | case TSP_FID_SUB: |
| 334 | results[0] -= service_args[0]; |
| 335 | results[1] -= service_args[1]; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 336 | break; |
| 337 | case TSP_FID_MUL: |
| 338 | results[0] *= service_args[0]; |
| 339 | results[1] *= service_args[1]; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 340 | break; |
| 341 | case TSP_FID_DIV: |
| 342 | results[0] /= service_args[0] ? service_args[0] : 1; |
| 343 | results[1] /= service_args[1] ? service_args[1] : 1; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 344 | break; |
| 345 | default: |
| 346 | break; |
| 347 | } |
| 348 | |
Achin Gupta | 916a2c1 | 2014-02-09 23:11:46 +0000 | [diff] [blame] | 349 | return set_smc_args(func, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 350 | results[0], |
| 351 | results[1], |
Achin Gupta | 916a2c1 | 2014-02-09 23:11:46 +0000 | [diff] [blame] | 352 | 0, 0, 0, 0, 0); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 353 | } |
| 354 | |