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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Build Options
2=============
3
4The TF-A build system supports the following build options. Unless mentioned
5otherwise, these options are expected to be specified at the build command
6line and are not to be modified in any component makefiles. Note that the
7build system doesn't track dependency for build options. Therefore, if any of
8the build options are changed from a previous build, a clean build must be
9performed.
10
11.. _build_options_common:
12
13Common build options
14--------------------
15
16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
18 code having a smaller resulting size.
19
20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
22 directory containing the SP source, relative to the ``bl32/``; the directory
23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
24
johpow01fa59c6f2020-10-02 13:41:11 -050025- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
26 zero at all but the highest implemented exception level. Reads from the
27 memory mapped view are unaffected by this control.
28
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010029- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
31 ``aarch64``.
32
Alexei Fedorov132e6652020-12-07 16:38:53 +000033- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies
34 one or more feature modifiers. This option has the form ``[no]feature+...``
35 and defaults to ``none``. It translates into compiler option
36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the
37 list of supported feature modifiers.
38
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010039- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
42 :ref:`Firmware Design`.
43
44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
47
48- ``BL2``: This is an optional build option which specifies the path to BL2
49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
50 built.
51
52- ``BL2U``: This is an optional build option which specifies the path to
53 BL2U image. In this case, the BL2U in TF-A will not be built.
54
55- ``BL2_AT_EL3``: This is an optional build option that enables the use of
56 BL2 at EL3 execution level.
57
58- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
59 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
60 the RW sections in RAM, while leaving the RO sections in place. This option
61 enable this use-case. For now, this option is only supported when BL2_AT_EL3
62 is set to '1'.
63
64- ``BL31``: This is an optional build option which specifies the path to
65 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
66 be built.
67
68- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
69 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
70 this file name will be used to save the key.
71
72- ``BL32``: This is an optional build option which specifies the path to
73 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
74 be built.
75
76- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
77 Trusted OS Extra1 image for the ``fip`` target.
78
79- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
80 Trusted OS Extra2 image for the ``fip`` target.
81
82- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
83 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
84 this file name will be used to save the key.
85
86- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
87 ``fip`` target in case TF-A BL2 is used.
88
89- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
90 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
91 this file name will be used to save the key.
92
93- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
94 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
95 If enabled, it is needed to use a compiler that supports the option
96 ``-mbranch-protection``. Selects the branch protection features to use:
97- 0: Default value turns off all types of branch protection
98- 1: Enables all types of branch protection features
99- 2: Return address signing to its standard level
100- 3: Extend the signing to include leaf functions
Alexei Fedorove039e482020-06-19 14:33:49 +0100101- 4: Turn on branch target identification mechanism
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100102
103 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
104 and resulting PAuth/BTI features.
105
106 +-------+--------------+-------+-----+
107 | Value | GCC option | PAuth | BTI |
108 +=======+==============+=======+=====+
109 | 0 | none | N | N |
110 +-------+--------------+-------+-----+
111 | 1 | standard | Y | Y |
112 +-------+--------------+-------+-----+
113 | 2 | pac-ret | Y | N |
114 +-------+--------------+-------+-----+
115 | 3 | pac-ret+leaf | Y | N |
116 +-------+--------------+-------+-----+
Alexei Fedorove039e482020-06-19 14:33:49 +0100117 | 4 | bti | N | Y |
118 +-------+--------------+-------+-----+
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100119
120 This option defaults to 0 and this is an experimental feature.
121 Note that Pointer Authentication is enabled for Non-secure world
122 irrespective of the value of this option if the CPU supports it.
123
124- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
125 compilation of each build. It must be set to a C string (including quotes
126 where applicable). Defaults to a string that contains the time and date of
127 the compilation.
128
129- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
130 build to be uniquely identified. Defaults to the current git commit id.
131
Grant Likely388248a2020-07-30 08:50:10 +0100132- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build``
133
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100134- ``CFLAGS``: Extra user options appended on the compiler's command line in
135 addition to the options set by the build system.
136
137- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
138 release several CPUs out of reset. It can take either 0 (several CPUs may be
139 brought up) or 1 (only one CPU will ever be brought up during cold reset).
140 Default is 0. If the platform always brings up a single CPU, there is no
141 need to distinguish between primary and secondary CPUs and the boot path can
142 be optimised. The ``plat_is_my_cpu_primary()`` and
143 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
144 to be implemented in this case.
145
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100146- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
147 Defaults to ``tbbr``.
148
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100149- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
150 register state when an unexpected exception occurs during execution of
151 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
152 this is only enabled for a debug build of the firmware.
153
154- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
155 certificate generation tool to create new keys in case no valid keys are
156 present or specified. Allowed options are '0' or '1'. Default is '1'.
157
158- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
159 the AArch32 system registers to be included when saving and restoring the
160 CPU context. The option must be set to 0 for AArch64-only platforms (that
161 is on hardware that does not implement AArch32, or at least not at EL1 and
162 higher ELs). Default value is 1.
163
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100164- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore
165 operations when entering/exiting an EL2 execution context. This is of primary
166 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled).
167 This option must be equal to 1 (enabled) when ``SPD=spmd`` and
168 ``SPMD_SPM_AT_SEL2`` is set.
169
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100170- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
171 registers to be included when saving and restoring the CPU context. Default
172 is 0.
173
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +0100174- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the
175 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2
176 execution context. Default value is 0.
177
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100178- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
179 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
180 registers to be included when saving and restoring the CPU context as
181 part of world switch. Default value is 0 and this is an experimental feature.
182 Note that Pointer Authentication is enabled for Non-secure world irrespective
183 of the value of this flag if the CPU supports it.
184
185- ``DEBUG``: Chooses between a debug and release build. It can take either 0
186 (release) or 1 (debug) as values. 0 is the default.
187
Sumit Garg392e4df2019-11-15 10:43:00 +0530188- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the
189 authenticated decryption algorithm to be used to decrypt firmware/s during
190 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of
191 this flag is ``none`` to disable firmware decryption which is an optional
192 feature as per TBBR. Also, it is an experimental feature.
193
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100194- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
195 of the binary image. If set to 1, then only the ELF image is built.
196 0 is the default.
197
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000198- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented
199 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms
200 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU,
201 check the latest Arm ARM.
202
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100203- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
204 Board Boot authentication at runtime. This option is meant to be enabled only
205 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
206 flag has to be enabled. 0 is the default.
207
208- ``E``: Boolean option to make warnings into errors. Default is 1.
209
210- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
211 the normal boot flow. It must specify the entry point address of the EL3
212 payload. Please refer to the "Booting an EL3 payload" section for more
213 details.
214
215- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
216 This is an optional architectural feature available on v8.4 onwards. Some
217 v8.2 implementations also implement an AMU and this option can be used to
218 enable this feature on those systems as well. Default is 0.
219
220- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
221 are compiled out. For debug builds, this option defaults to 1, and calls to
222 ``assert()`` are left in place. For release builds, this option defaults to 0
223 and calls to ``assert()`` function are compiled out. This option can be set
224 independently of ``DEBUG``. It can also be used to hide any auxiliary code
225 that is only required for the assertion and does not fit in the assertion
226 itself.
227
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000228- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100229 dumps or not. It is supported in both AArch64 and AArch32. However, in
230 AArch32 the format of the frame records are not defined in the AAPCS and they
231 are defined by the implementation. This implementation of backtrace only
232 supports the format used by GCC when T32 interworking is disabled. For this
233 reason enabling this option in AArch32 will force the compiler to only
234 generate A32 code. This option is enabled by default only in AArch64 debug
235 builds, but this behaviour can be overridden in each platform's Makefile or
236 in the build command line.
237
Sandrine Bailleux11427302019-12-17 09:38:08 +0100238- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
zelalem-aweked5f45272019-11-12 16:20:17 -0600239 support in GCC for TF-A. This option is currently only supported for
240 AArch64. Default is 0.
241
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100242- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
243 feature. MPAM is an optional Armv8.4 extension that enables various memory
244 system components and resources to define partitions; software running at
245 various ELs can assign themselves to desired partition to control their
246 performance aspects.
247
248 When this option is set to ``1``, EL3 allows lower ELs to access their own
249 MPAM registers without trapping into EL3. This option doesn't make use of
250 partitioning in EL3, however. Platform initialisation code should configure
251 and use partitions in EL3 as required. This option defaults to ``0``.
252
253- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
254 support within generic code in TF-A. This option is currently only supported
Yann Gautier514e59c2020-10-05 11:02:54 +0200255 in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32
256 (SP_min) for AARCH32. Default is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100257
258- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
259 Measurement Framework(PMF). Default is 0.
260
261- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
262 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
263 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
264 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
265 software.
266
267- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
268 instrumentation which injects timestamp collection points into TF-A to
269 allow runtime performance to be measured. Currently, only PSCI is
270 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
271 as well. Default is 0.
272
273- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
274 extensions. This is an optional architectural feature for AArch64.
275 The default is 1 but is automatically disabled when the target architecture
276 is AArch32.
277
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100278- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
279 (SVE) for the Non-secure world only. SVE is an optional architectural feature
280 for AArch64. Note that when SVE is enabled for the Non-secure world, access
Max Shvetsovc4502772021-03-22 11:59:37 +0000281 to SIMD and floating-point functionality from the Secure world is disabled by
282 default and controlled with ENABLE_SVE_FOR_SWD.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100283 This is to avoid corruption of the Non-secure world data in the Z-registers
284 which are aliased by the SIMD and FP registers. The build option is not
285 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
286 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
287 1. The default is 1 but is automatically disabled when the target
288 architecture is AArch32.
289
Max Shvetsovc4502772021-03-22 11:59:37 +0000290- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
291 SVE is an optional architectural feature for AArch64. Note that this option
292 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is
293 automatically disabled when the target architecture is AArch32.
294
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100295- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
296 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
297 default value is set to "none". "strong" is the recommended stack protection
298 level if this feature is desired. "none" disables the stack protection. For
299 all values other than "none", the ``plat_get_stack_protector_canary()``
300 platform hook needs to be implemented. The value is passed as the last
301 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
302
Sumit Gargc0c369c2019-11-15 18:47:53 +0530303- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This
304 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as
305 experimental.
306
307- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload.
308 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as
309 experimental.
310
311- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could
312 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends
313 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental.
314
315- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector
316 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT``
317 build flag which is marked as experimental.
318
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100319- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
320 deprecated platform APIs, helper functions or drivers within Trusted
321 Firmware as error. It can take the value 1 (flag the use of deprecated
322 APIs as error) or 0. The default is 0.
323
324- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
325 targeted at EL3. When set ``0`` (default), no exceptions are expected or
326 handled at EL3, and a panic will result. This is supported only for AArch64
327 builds.
328
Javier Almansa Sobrino0d1f6b12020-09-18 16:47:07 +0100329- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when
330 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``.
331 Default value is 40 (LOG_LEVEL_INFO).
332
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100333- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
334 injection from lower ELs, and this build option enables lower ELs to use
335 Error Records accessed via System Registers to inject faults. This is
336 applicable only to AArch64 builds.
337
338 This feature is intended for testing purposes only, and is advisable to keep
339 disabled for production images.
340
341- ``FIP_NAME``: This is an optional build option which specifies the FIP
342 filename for the ``fip`` target. Default is ``fip.bin``.
343
344- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
345 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
346
Sumit Gargc0c369c2019-11-15 18:47:53 +0530347- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values:
348
349 ::
350
351 0: Encryption is done with Secret Symmetric Key (SSK) which is common
352 for a class of devices.
353 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is
354 unique per device.
355
356 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as
357 experimental.
358
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100359- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
360 tool to create certificates as per the Chain of Trust described in
361 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
362 include the certificates in the FIP and FWU_FIP. Default value is '0'.
363
364 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
365 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
366 the corresponding certificates, and to include those certificates in the
367 FIP and FWU_FIP.
368
369 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
370 images will not include support for Trusted Board Boot. The FIP will still
371 include the corresponding certificates. This FIP can be used to verify the
372 Chain of Trust on the host machine through other mechanisms.
373
374 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
375 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
376 will not include the corresponding certificates, causing a boot failure.
377
378- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
379 inherent support for specific EL3 type interrupts. Setting this build option
380 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500381 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and
382 :ref:`Interrupt Management Framework<Interrupt Management Framework>`.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100383 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
384 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
385 the Secure Payload interrupts needs to be synchronously handed over to Secure
386 EL1 for handling. The default value of this option is ``0``, which means the
387 Group 0 interrupts are assumed to be handled by Secure EL1.
388
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100389- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
390 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
391 ``0`` (default), these exceptions will be trapped in the current exception
392 level (or in EL1 if the current exception level is EL0).
393
394- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
395 software operations are required for CPUs to enter and exit coherency.
396 However, newer systems exist where CPUs' entry to and exit from coherency
397 is managed in hardware. Such systems require software to only initiate these
398 operations, and the rest is managed in hardware, minimizing active software
399 management. In such systems, this boolean option enables TF-A to carry out
400 build and run-time optimizations during boot and power management operations.
401 This option defaults to 0 and if it is enabled, then it implies
402 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
403
404 If this flag is disabled while the platform which TF-A is compiled for
405 includes cores that manage coherency in hardware, then a compilation error is
406 generated. This is based on the fact that a system cannot have, at the same
407 time, cores that manage coherency in hardware and cores that don't. In other
408 words, a platform cannot have, at the same time, cores that require
409 ``HW_ASSISTED_COHERENCY=1`` and cores that require
410 ``HW_ASSISTED_COHERENCY=0``.
411
412 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
413 translation library (xlat tables v2) must be used; version 1 of translation
414 library is not supported.
415
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000416- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000417 bottom, higher addresses at the top. This build flag can be set to '1' to
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000418 invert this behavior. Lower addresses will be printed at the top and higher
419 addresses at the bottom.
420
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100421- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
422 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
423 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
424 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
425 images.
426
427- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
428 used for generating the PKCS keys and subsequent signing of the certificate.
429 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
430 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
431 compliant and is retained only for compatibility. The default value of this
432 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
433
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300434- ``KEY_SIZE``: This build flag enables the user to select the key size for
435 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
436 depend on the chosen algorithm and the cryptographic module.
437
438 +-----------+------------------------------------+
439 | KEY_ALG | Possible key sizes |
440 +===========+====================================+
441 | rsa | 1024 , 2048 (default), 3072, 4096* |
442 +-----------+------------------------------------+
443 | ecdsa | unavailable |
444 +-----------+------------------------------------+
445
446 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
447 Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
448
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100449- ``HASH_ALG``: This build flag enables the user to select the secure hash
450 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
451 The default value of this flag is ``sha256``.
452
453- ``LDFLAGS``: Extra user options appended to the linkers' command line in
454 addition to the one set by the build system.
455
456- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
457 output compiled into the build. This should be one of the following:
458
459 ::
460
461 0 (LOG_LEVEL_NONE)
462 10 (LOG_LEVEL_ERROR)
463 20 (LOG_LEVEL_NOTICE)
464 30 (LOG_LEVEL_WARNING)
465 40 (LOG_LEVEL_INFO)
466 50 (LOG_LEVEL_VERBOSE)
467
468 All log output up to and including the selected log level is compiled into
469 the build. The default value is 40 in debug builds and 20 in release builds.
470
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000471- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
Sandrine Bailleux533d8b32021-06-10 11:18:04 +0200472 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well
473 in order to provide trust that the code taking the measurements and recording
474 them has not been tampered with.
475
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000476 This option defaults to 0 and is an experimental feature in the stage of
477 development.
478
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100479- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
480 specifies the file that contains the Non-Trusted World private key in PEM
481 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
482
483- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
484 optional. It is only needed if the platform makefile specifies that it
485 is required in order to build the ``fwu_fip`` target.
486
487- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
488 contents upon world switch. It can take either 0 (don't save and restore) or
489 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
490 wants the timer registers to be saved and restored.
491
492- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
493 for the BL image. It can be either 0 (include) or 1 (remove). The default
494 value is 0.
495
496- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
497 the underlying hardware is not a full PL011 UART but a minimally compliant
498 generic UART, which is a subset of the PL011. The driver will not access
499 any register that is not part of the SBSA generic UART specification.
500 Default value is 0 (a full PL011 compliant UART is present).
501
502- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
503 must be subdirectory of any depth under ``plat/``, and must contain a
504 platform makefile named ``platform.mk``. For example, to build TF-A for the
505 Arm Juno board, select PLAT=juno.
506
507- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
508 instead of the normal boot flow. When defined, it must specify the entry
509 point address for the preloaded BL33 image. This option is incompatible with
510 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
511 over ``PRELOADED_BL33_BASE``.
512
513- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
514 vector address can be programmed or is fixed on the platform. It can take
515 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
516 programmable reset address, it is expected that a CPU will start executing
517 code directly at the right address, both on a cold and warm reset. In this
518 case, there is no need to identify the entrypoint on boot and the boot path
519 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
520 does not need to be implemented in this case.
521
522- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
523 possible for the PSCI power-state parameter: original and extended State-ID
524 formats. This flag if set to 1, configures the generic PSCI layer to use the
525 extended format. The default value of this flag is 0, which means by default
526 the original power-state format is used by the PSCI implementation. This flag
527 should be specified by the platform makefile and it governs the return value
528 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
529 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
530 set to 1 as well.
531
532- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
533 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
534 or later CPUs.
535
536 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
537 set to ``1``.
538
539 This option is disabled by default.
540
541- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
542 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
543 entrypoint) or 1 (CPU reset to BL31 entrypoint).
544 The default value is 0.
545
546- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
547 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
548 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
549 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
550
551- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Max Shvetsov06dba292019-12-06 11:50:12 +0000552 file that contains the ROT private key in PEM format and enforces public key
553 hash generation. If ``SAVE_KEYS=1``, this
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100554 file name will be used to save the key.
555
556- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
557 certificate generation tool to save the keys used to establish the Chain of
558 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
559
560- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
561 If a SCP_BL2 image is present then this option must be passed for the ``fip``
562 target.
563
564- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
565 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
566 this file name will be used to save the key.
567
568- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
569 optional. It is only needed if the platform makefile specifies that it
570 is required in order to build the ``fwu_fip`` target.
571
572- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
573 Delegated Exception Interface to BL31 image. This defaults to ``0``.
574
575 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
576 set to ``1``.
577
578- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
579 isolated on separate memory pages. This is a trade-off between security and
580 memory usage. See "Isolating code and read-only data on separate memory
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100581 pages" section in :ref:`Firmware Design`. This flag is disabled by default
582 and affects all BL images.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100583
Samuel Holland31a14e12018-10-17 21:40:18 -0500584- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
585 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
586 allocated in RAM discontiguous from the loaded firmware image. When set, the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000587 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
Samuel Holland31a14e12018-10-17 21:40:18 -0500588 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
589 sections are placed in RAM immediately following the loaded firmware image.
590
Jeremy Linton684a0792021-01-26 22:42:03 -0600591- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
592 access requests via a standard SMCCC defined in `DEN0115`_. When combined with
593 UEFI+ACPI this can provide a certain amount of OS forward compatibility
594 with newer platforms that aren't ECAM compliant.
595
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100596- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
597 This build option is only valid if ``ARCH=aarch64``. The value should be
598 the path to the directory containing the SPD source, relative to
599 ``services/spd/``; the directory is expected to contain a makefile called
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100600 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in
601 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher
602 cannot be enabled when the ``SPM_MM`` option is enabled.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100603
604- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
605 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
606 execution in BL1 just before handing over to BL31. At this point, all
607 firmware images have been loaded in memory, and the MMU and caches are
608 turned off. Refer to the "Debugging options" section for more details.
609
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100610- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM
611 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
612 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2
613 extension. This is the default when enabling the SPM Dispatcher. When
614 disabled (0) it indicates the SPMC component runs at the S-EL1 execution
615 state. This latter configuration supports pre-Armv8.4 platforms (aka not
616 implementing the Armv8.4-SecEL2 extension).
617
Paul Beesleyfe975b42019-09-16 11:29:03 +0000618- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100619 Partition Manager (SPM) implementation. The default value is ``0``
620 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
621 enabled (``SPD=spmd``).
Paul Beesleyfe975b42019-09-16 11:29:03 +0000622
Manish Pandey3f90ad72020-01-14 11:52:05 +0000623- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100624 description of secure partitions. The build system will parse this file and
625 package all secure partition blobs into the FIP. This file is not
626 necessarily part of TF-A tree. Only available when ``SPD=spmd``.
Manish Pandey3f90ad72020-01-14 11:52:05 +0000627
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100628- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
629 secure interrupts (caught through the FIQ line). Platforms can enable
630 this directive if they need to handle such interruption. When enabled,
631 the FIQ are handled in monitor mode and non secure world is not allowed
632 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
633 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
634
635- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
636 Boot feature. When set to '1', BL1 and BL2 images include support to load
637 and verify the certificates and images in a FIP, and BL1 includes support
638 for the Firmware Update. The default value is '0'. Generation and inclusion
639 of certificates in the FIP and FWU_FIP depends upon the value of the
640 ``GENERATE_COT`` option.
641
642 .. warning::
643 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
644 already exist in disk, they will be overwritten without further notice.
645
646- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
647 specifies the file that contains the Trusted World private key in PEM
648 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
649
650- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
651 synchronous, (see "Initializing a BL32 Image" section in
652 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
653 synchronous method) or 1 (BL32 is initialized using asynchronous method).
654 Default is 0.
655
656- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
657 routing model which routes non-secure interrupts asynchronously from TSP
658 to EL3 causing immediate preemption of TSP. The EL3 is responsible
659 for saving and restoring the TSP context in this routing model. The
660 default routing model (when the value is 0) is to route non-secure
661 interrupts to TSP allowing it to save its context and hand over
662 synchronously to EL3 via an SMC.
663
664 .. note::
665 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
666 must also be set to ``1``.
667
668- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
669 linker. When the ``LINKER`` build variable points to the armlink linker,
670 this flag is enabled automatically. To enable support for armlink, platforms
671 will have to provide a scatter file for the BL image. Currently, Tegra
672 platforms use the armlink support to compile BL3-1 images.
673
674- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
675 memory region in the BL memory map or not (see "Use of Coherent memory in
676 TF-A" section in :ref:`Firmware Design`). It can take the value 1
677 (Coherent memory region is included) or 0 (Coherent memory region is
678 excluded). Default is 1.
679
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100680- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature
681 exposing a virtual filesystem interface through BL31 as a SiP SMC function.
682 Default is 0.
683
Louis Mayencourt6b232d92020-02-28 16:57:30 +0000684- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
685 firmware configuration framework. This will move the io_policies into a
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100686 configuration device tree, instead of static structure in the code base.
Louis Mayencourtb25b8b62020-04-09 16:32:20 +0100687 This is currently an experimental feature.
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100688
Manish V Badarkhead339892020-06-29 10:32:53 +0100689- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors
690 at runtime using fconf. If this flag is enabled, COT descriptors are
691 statically captured in tb_fw_config file in the form of device tree nodes
692 and properties. Currently, COT descriptors used by BL2 are moved to the
693 device tree and COT descriptors used by BL1 are retained in the code
694 base statically. This is currently an experimental feature.
695
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100696- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in
697 runtime using firmware configuration framework. The platform specific SDEI
698 shared and private events configuration is retrieved from device tree rather
699 than static C structures at compile time. This is currently an experimental
700 feature and is only supported if SDEI_SUPPORT build flag is enabled.
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100701
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500702- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0
703 and Group1 secure interrupts using the firmware configuration framework. The
704 platform specific secure interrupt property descriptor is retrieved from
705 device tree in runtime rather than depending on static C structure at compile
706 time. This is currently an experimental feature.
707
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100708- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
709 This feature creates a library of functions to be placed in ROM and thus
710 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
711 is 0.
712
713- ``V``: Verbose build. If assigned anything other than 0, the build commands
714 are printed. Default is 0.
715
716- ``VERSION_STRING``: String used in the log output for each TF-A image.
717 Defaults to a string formed by concatenating the version number, build type
718 and build string.
719
720- ``W``: Warning level. Some compiler warning options of interest have been
721 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
722 each level enabling more warning options. Default is 0.
723
724- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
725 the CPU after warm boot. This is applicable for platforms which do not
726 require interconnect programming to enable cache coherency (eg: single
727 cluster platforms). If this option is enabled, then warm boot path
728 enables D-caches immediately after enabling MMU. This option defaults to 0.
729
Manish V Badarkhe75c972a2020-03-22 05:06:38 +0000730- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
731 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
732 default value of this flag is ``no``. Note this option must be enabled only
733 for ARM architecture greater than Armv8.5-A.
734
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100735- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
736 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
737 The default value of this flag is ``0``.
738
739 ``AT`` speculative errata workaround disables stage1 page table walk for
740 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point
741 produces either the correct result or failure without TLB allocation.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100742
743 This boolean option enables errata for all below CPUs.
744
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100745 +---------+--------------+-------------------------+
746 | Errata | CPU | Workaround Define |
747 +=========+==============+=========================+
748 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` |
749 +---------+--------------+-------------------------+
750 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` |
751 +---------+--------------+-------------------------+
752 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` |
753 +---------+--------------+-------------------------+
754 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` |
755 +---------+--------------+-------------------------+
756 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` |
757 +---------+--------------+-------------------------+
758
759 .. note::
760 This option is enabled by build only if platform sets any of above defines
761 mentioned in ’Workaround Define' column in the table.
762 If this option is enabled for the EL3 software then EL2 software also must
763 implement this workaround due to the behaviour of the errata mentioned
764 in new SDEN document which will get published soon.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100765
Varun Wadekar92234852020-06-12 10:11:28 -0700766- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR
767 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
768 This flag is disabled by default.
769
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100770- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory
771 path on the host machine which is used to build certificate generation and
772 firmware encryption tool.
773
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500774- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for
775 functions that wait for an arbitrary time length (udelay and mdelay). The
776 default value is 0.
777
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000778GICv3 driver options
779--------------------
780
781GICv3 driver files are included using directive:
782
783``include drivers/arm/gic/v3/gicv3.mk``
784
785The driver can be configured with the following options set in the platform
786makefile:
787
Andre Przywarae1cc1302020-03-25 15:50:38 +0000788- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3.
789 Enabling this option will add runtime detection support for the
790 GIC-600, so is safe to select even for a GIC500 implementation.
791 This option defaults to 0.
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000792
793- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip
794 functionality. This option defaults to 0
795
796- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation
797 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore``
798 functions. This is required for FVP platform which need to simulate GIC save
799 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
800
Alexei Fedorov19705932020-04-06 19:00:35 +0100801- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver.
802 This option defaults to 0.
803
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100804- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended
805 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.
806
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100807Debugging options
808-----------------
809
810To compile a debug version and make the build more verbose use
811
812.. code:: shell
813
814 make PLAT=<platform> DEBUG=1 V=1 all
815
816AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
817example DS-5) might not support this and may need an older version of DWARF
818symbols to be emitted by GCC. This can be achieved by using the
819``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
820version to 2 is recommended for DS-5 versions older than 5.16.
821
822When debugging logic problems it might also be useful to disable all compiler
823optimizations by using ``-O0``.
824
825.. warning::
826 Using ``-O0`` could cause output images to be larger and base addresses
827 might need to be recalculated (see the **Memory layout on Arm development
828 platforms** section in the :ref:`Firmware Design`).
829
830Extra debug options can be passed to the build system by setting ``CFLAGS`` or
831``LDFLAGS``:
832
833.. code:: shell
834
835 CFLAGS='-O0 -gdwarf-2' \
836 make PLAT=<platform> DEBUG=1 V=1 all
837
838Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
839ignored as the linker is called directly.
840
841It is also possible to introduce an infinite loop to help in debugging the
842post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
843``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
844section. In this case, the developer may take control of the target using a
845debugger when indicated by the console output. When using DS-5, the following
846commands can be used:
847
848::
849
850 # Stop target execution
851 interrupt
852
853 #
854 # Prepare your debugging environment, e.g. set breakpoints
855 #
856
857 # Jump over the debug loop
858 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
859
860 # Resume execution
861 continue
862
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +0000863Firmware update options
864-----------------------
865
866- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used
867 in defining the firmware update metadata structure. This flag is by default
868 set to '2'.
869
870- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each
871 firmware bank. Each firmware bank must have the same number of images as per
872 the `PSA FW update specification`_.
873 This flag is used in defining the firmware update metadata structure. This
874 flag is by default set to '1'.
875
Manish V Badarkheda87af12021-06-20 21:14:46 +0100876- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the
877 `PSA FW update specification`_. The default value is 0, and this is an
878 experimental feature.
879 PSA firmware update implementation has some limitations, such as BL2 is
880 not part of the protocol-updatable images, if BL2 needs to be updated, then
881 it should be done through another platform-defined mechanism, and it assumes
882 that the platform's hardware supports CRC32 instructions.
883
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100884--------------
885
Yann Gautier514e59c2020-10-05 11:02:54 +0200886*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
Jeremy Linton684a0792021-01-26 22:42:03 -0600887
888.. _DEN0115: https://developer.arm.com/docs/den0115/latest
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +0000889.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
Jeremy Linton684a0792021-01-26 22:42:03 -0600890