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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Antonio Nino Diazc326c342019-01-11 11:20:10 +00002 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef ARCH_H
8#define ARCH_H
Soby Mathewc6820d12016-05-09 17:49:55 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Isla Mitchell02c63072017-07-21 14:44:36 +010011
Soby Mathewc6820d12016-05-09 17:49:55 +010012/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(24)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_REV_SHIFT U(0)
20#define MIDR_REV_BITS U(4)
21#define MIDR_PN_MASK U(0xfff)
22#define MIDR_PN_SHIFT U(4)
Soby Mathewc6820d12016-05-09 17:49:55 +010023
24/*******************************************************************************
25 * MPIDR macros
26 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010027#define MPIDR_MT_MASK (U(1) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +010028#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
29#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_AFFINITY_BITS U(8)
31#define MPIDR_AFFLVL_MASK U(0xff)
32#define MPIDR_AFFLVL_SHIFT U(3)
33#define MPIDR_AFF0_SHIFT U(0)
34#define MPIDR_AFF1_SHIFT U(8)
35#define MPIDR_AFF2_SHIFT U(16)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000036#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010037#define MPIDR_AFFINITY_MASK U(0x00ffffff)
38#define MPIDR_AFFLVL0 U(0)
39#define MPIDR_AFFLVL1 U(1)
40#define MPIDR_AFFLVL2 U(2)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000041#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Soby Mathewc6820d12016-05-09 17:49:55 +010042
43#define MPIDR_AFFLVL0_VAL(mpidr) \
44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
45#define MPIDR_AFFLVL1_VAL(mpidr) \
46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
47#define MPIDR_AFFLVL2_VAL(mpidr) \
48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010049#define MPIDR_AFFLVL3_VAL(mpidr) U(0)
Soby Mathewc6820d12016-05-09 17:49:55 +010050
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000051#define MPIDR_AFF_ID(mpid, n) \
52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
53
54#define MPID_MASK (MPIDR_MT_MASK |\
55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
58
59/*
60 * An invalid MPID. This value can be used by functions that return an MPID to
61 * indicate an error.
62 */
63#define INVALID_MPID U(0xFFFFFFFF)
64
Soby Mathewc6820d12016-05-09 17:49:55 +010065/*
66 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
67 * add one while using this macro to define array sizes.
68 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010069#define MPIDR_MAX_AFFLVL U(2)
Soby Mathewc6820d12016-05-09 17:49:55 +010070
71/* Data Cache set/way op type defines */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010072#define DC_OP_ISW U(0x0)
73#define DC_OP_CISW U(0x1)
74#define DC_OP_CSW U(0x2)
Soby Mathewc6820d12016-05-09 17:49:55 +010075
76/*******************************************************************************
77 * Generic timer memory mapped registers & offsets
78 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010079#define CNTCR_OFF U(0x000)
80#define CNTFID_OFF U(0x020)
Soby Mathewc6820d12016-05-09 17:49:55 +010081
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010082#define CNTCR_EN (U(1) << 0)
83#define CNTCR_HDBG (U(1) << 1)
Soby Mathewc6820d12016-05-09 17:49:55 +010084#define CNTCR_FCREQ(x) ((x) << 8)
85
86/*******************************************************************************
87 * System register bit definitions
88 ******************************************************************************/
89/* CLIDR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010090#define LOUIS_SHIFT U(21)
91#define LOC_SHIFT U(24)
92#define CLIDR_FIELD_WIDTH U(3)
Soby Mathewc6820d12016-05-09 17:49:55 +010093
94/* CSSELR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010095#define LEVEL_SHIFT U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +010096
Antonio Nino Diazc326c342019-01-11 11:20:10 +000097/* ID_MMFR4 definitions */
98#define ID_MMFR4_CNP_SHIFT U(12)
99#define ID_MMFR4_CNP_LENGTH U(4)
100#define ID_MMFR4_CNP_MASK U(0xf)
101
102/* ID_PFR0 definitions */
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100103#define ID_PFR0_AMU_SHIFT U(20)
104#define ID_PFR0_AMU_LENGTH U(4)
105#define ID_PFR0_AMU_MASK U(0xf)
106
Sathees Balya0911df12018-12-06 13:33:24 +0000107#define ID_PFR0_DIT_SHIFT U(24)
108#define ID_PFR0_DIT_LENGTH U(4)
109#define ID_PFR0_DIT_MASK U(0xf)
110#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
111
Soby Mathewc6820d12016-05-09 17:49:55 +0100112/* ID_PFR1 definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100113#define ID_PFR1_VIRTEXT_SHIFT U(12)
114#define ID_PFR1_VIRTEXT_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100115#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
116 & ID_PFR1_VIRTEXT_MASK)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100117#define ID_PFR1_GIC_SHIFT U(28)
118#define ID_PFR1_GIC_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100119
120/* SCTLR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100121#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
122 (U(1) << 3))
Etienne Carriere70a004b2017-11-05 22:56:03 +0100123#if ARM_ARCH_MAJOR == 7
124#define SCTLR_RES1 SCTLR_RES1_DEF
125#else
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100126#define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
Etienne Carriere70a004b2017-11-05 22:56:03 +0100127#endif
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100128#define SCTLR_M_BIT (U(1) << 0)
129#define SCTLR_A_BIT (U(1) << 1)
130#define SCTLR_C_BIT (U(1) << 2)
131#define SCTLR_CP15BEN_BIT (U(1) << 5)
132#define SCTLR_ITD_BIT (U(1) << 7)
133#define SCTLR_Z_BIT (U(1) << 11)
134#define SCTLR_I_BIT (U(1) << 12)
135#define SCTLR_V_BIT (U(1) << 13)
136#define SCTLR_RR_BIT (U(1) << 14)
137#define SCTLR_NTWI_BIT (U(1) << 16)
138#define SCTLR_NTWE_BIT (U(1) << 18)
139#define SCTLR_WXN_BIT (U(1) << 19)
140#define SCTLR_UWXN_BIT (U(1) << 20)
141#define SCTLR_EE_BIT (U(1) << 25)
142#define SCTLR_TRE_BIT (U(1) << 28)
143#define SCTLR_AFE_BIT (U(1) << 29)
144#define SCTLR_TE_BIT (U(1) << 30)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000145#define SCTLR_DSSBS_BIT (U(1) << 31)
David Cunadofee86532017-04-13 22:38:29 +0100146#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
147 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
Soby Mathewc6820d12016-05-09 17:49:55 +0100148
dp-arm595d0d52017-02-08 11:51:50 +0000149/* SDCR definitions */
150#define SDCR_SPD(x) ((x) << 14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100151#define SDCR_SPD_LEGACY U(0x0)
152#define SDCR_SPD_DISABLE U(0x2)
153#define SDCR_SPD_ENABLE U(0x3)
154#define SDCR_RESET_VAL U(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000155
Soby Mathewc6820d12016-05-09 17:49:55 +0100156/* HSCTLR definitions */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000157#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100158 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
159 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
160
161#define HSCTLR_M_BIT (U(1) << 0)
162#define HSCTLR_A_BIT (U(1) << 1)
163#define HSCTLR_C_BIT (U(1) << 2)
164#define HSCTLR_CP15BEN_BIT (U(1) << 5)
165#define HSCTLR_ITD_BIT (U(1) << 7)
166#define HSCTLR_SED_BIT (U(1) << 8)
167#define HSCTLR_I_BIT (U(1) << 12)
168#define HSCTLR_WXN_BIT (U(1) << 19)
169#define HSCTLR_EE_BIT (U(1) << 25)
170#define HSCTLR_TE_BIT (U(1) << 30)
Soby Mathewc6820d12016-05-09 17:49:55 +0100171
172/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100173#define CPACR_FPEN(x) ((x) << 20)
174#define CPACR_FP_TRAP_PL0 U(0x1)
175#define CPACR_FP_TRAP_ALL U(0x2)
176#define CPACR_FP_TRAP_NONE U(0x3)
Soby Mathewc6820d12016-05-09 17:49:55 +0100177
178/* SCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100179#define SCR_TWE_BIT (U(1) << 13)
180#define SCR_TWI_BIT (U(1) << 12)
181#define SCR_SIF_BIT (U(1) << 9)
182#define SCR_HCE_BIT (U(1) << 8)
183#define SCR_SCD_BIT (U(1) << 7)
184#define SCR_NET_BIT (U(1) << 6)
185#define SCR_AW_BIT (U(1) << 5)
186#define SCR_FW_BIT (U(1) << 4)
187#define SCR_EA_BIT (U(1) << 3)
188#define SCR_FIQ_BIT (U(1) << 2)
189#define SCR_IRQ_BIT (U(1) << 1)
190#define SCR_NS_BIT (U(1) << 0)
191#define SCR_VALID_BIT_MASK U(0x33ff)
192#define SCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100193
194#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
195
196/* HCR definitions */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000197#define HCR_TGE_BIT (U(1) << 27)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100198#define HCR_AMO_BIT (U(1) << 5)
199#define HCR_IMO_BIT (U(1) << 4)
200#define HCR_FMO_BIT (U(1) << 3)
201#define HCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100202
203/* CNTHCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100204#define CNTHCTL_RESET_VAL U(0x0)
205#define PL1PCEN_BIT (U(1) << 1)
206#define PL1PCTEN_BIT (U(1) << 0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100207
208/* CNTKCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100209#define PL0PTEN_BIT (U(1) << 9)
210#define PL0VTEN_BIT (U(1) << 8)
211#define PL0PCTEN_BIT (U(1) << 0)
212#define PL0VCTEN_BIT (U(1) << 1)
213#define EVNTEN_BIT (U(1) << 2)
214#define EVNTDIR_BIT (U(1) << 3)
215#define EVNTI_SHIFT U(4)
216#define EVNTI_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100217
218/* HCPTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100219#define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
220#define TCPAC_BIT (U(1) << 31)
221#define TAM_BIT (U(1) << 30)
222#define TTA_BIT (U(1) << 20)
Sandrine Bailleux6061c452018-07-13 10:04:12 +0200223#define TCP11_BIT (U(1) << 11)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100224#define TCP10_BIT (U(1) << 10)
David Cunadofee86532017-04-13 22:38:29 +0100225#define HCPTR_RESET_VAL HCPTR_RES1
226
227/* VTTBR defintions */
228#define VTTBR_RESET_VAL ULL(0x0)
229#define VTTBR_VMID_MASK ULL(0xff)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100230#define VTTBR_VMID_SHIFT U(48)
231#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
232#define VTTBR_BADDR_SHIFT U(0)
David Cunadofee86532017-04-13 22:38:29 +0100233
234/* HDCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100235#define HDCR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100236
237/* HSTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100238#define HSTR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100239
240/* CNTHP_CTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100241#define CNTHP_CTL_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100242
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000243/* NSACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100244#define NSASEDIS_BIT (U(1) << 15)
245#define NSTRCDIS_BIT (U(1) << 20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100246#define NSACR_CP11_BIT (U(1) << 11)
247#define NSACR_CP10_BIT (U(1) << 10)
248#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
David Cunadofee86532017-04-13 22:38:29 +0100249#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100250#define NSACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100251
252/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100253#define ASEDIS_BIT (U(1) << 31)
254#define TRCDIS_BIT (U(1) << 28)
255#define CPACR_CP11_SHIFT U(22)
256#define CPACR_CP10_SHIFT U(20)
257#define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
258 (U(0x3) << CPACR_CP10_SHIFT))
259#define CPACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100260
261/* FPEXC definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100262#define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
263#define FPEXC_EN_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100264#define FPEXC_RESET_VAL FPEXC_RES1
Soby Mathewc6820d12016-05-09 17:49:55 +0100265
266/* SPSR/CPSR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100267#define SPSR_FIQ_BIT (U(1) << 0)
268#define SPSR_IRQ_BIT (U(1) << 1)
269#define SPSR_ABT_BIT (U(1) << 2)
270#define SPSR_AIF_SHIFT U(6)
271#define SPSR_AIF_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100272
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100273#define SPSR_E_SHIFT U(9)
274#define SPSR_E_MASK U(0x1)
275#define SPSR_E_LITTLE U(0)
276#define SPSR_E_BIG U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100277
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100278#define SPSR_T_SHIFT U(5)
279#define SPSR_T_MASK U(0x1)
280#define SPSR_T_ARM U(0)
281#define SPSR_T_THUMB U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100282
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100283#define SPSR_MODE_SHIFT U(0)
284#define SPSR_MODE_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100285
286#define DISABLE_ALL_EXCEPTIONS \
287 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
288
Sathees Balya0911df12018-12-06 13:33:24 +0000289#define CPSR_DIT_BIT (U(1) << 21)
Soby Mathewc6820d12016-05-09 17:49:55 +0100290/*
291 * TTBCR definitions
292 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100293#define TTBCR_EAE_BIT (U(1) << 31)
Soby Mathewc6820d12016-05-09 17:49:55 +0100294
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100295#define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
296#define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
297#define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
Soby Mathewc6820d12016-05-09 17:49:55 +0100298
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100299#define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
300#define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
301#define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
302#define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
Soby Mathewc6820d12016-05-09 17:49:55 +0100303
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100304#define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
305#define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
306#define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
307#define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +0100308
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100309#define TTBCR_EPD1_BIT (U(1) << 23)
310#define TTBCR_A1_BIT (U(1) << 22)
Soby Mathewc6820d12016-05-09 17:49:55 +0100311
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100312#define TTBCR_T1SZ_SHIFT U(16)
313#define TTBCR_T1SZ_MASK U(0x7)
314#define TTBCR_TxSZ_MIN U(0)
315#define TTBCR_TxSZ_MAX U(7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100316
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100317#define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
318#define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
319#define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
Soby Mathewc6820d12016-05-09 17:49:55 +0100320
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100321#define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
322#define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
323#define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
324#define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
Soby Mathewc6820d12016-05-09 17:49:55 +0100325
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100326#define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
327#define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
328#define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
329#define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
Soby Mathewc6820d12016-05-09 17:49:55 +0100330
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100331#define TTBCR_EPD0_BIT (U(1) << 7)
332#define TTBCR_T0SZ_SHIFT U(0)
333#define TTBCR_T0SZ_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100334
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100335/*
336 * HTCR definitions
337 */
338#define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
339
340#define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
341#define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
342#define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
343
344#define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
345#define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
346#define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
347#define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
348
349#define HTCR_RGN0_INNER_NC (U(0x0) << 8)
350#define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
351#define HTCR_RGN0_INNER_WT (U(0x2) << 8)
352#define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
353
354#define HTCR_T0SZ_SHIFT U(0)
355#define HTCR_T0SZ_MASK U(0x7)
356
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100357#define MODE_RW_SHIFT U(0x4)
358#define MODE_RW_MASK U(0x1)
359#define MODE_RW_32 U(0x1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100360
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100361#define MODE32_SHIFT U(0)
362#define MODE32_MASK U(0x1f)
363#define MODE32_usr U(0x10)
364#define MODE32_fiq U(0x11)
365#define MODE32_irq U(0x12)
366#define MODE32_svc U(0x13)
367#define MODE32_mon U(0x16)
368#define MODE32_abt U(0x17)
369#define MODE32_hyp U(0x1a)
370#define MODE32_und U(0x1b)
371#define MODE32_sys U(0x1f)
Soby Mathewc6820d12016-05-09 17:49:55 +0100372
373#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
374
375#define SPSR_MODE32(mode, isa, endian, aif) \
376 (MODE_RW_32 << MODE_RW_SHIFT | \
377 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
378 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
379 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
380 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
381
382/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100383 * TTBR definitions
384 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100385#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100386
387/*
Soby Mathewc6820d12016-05-09 17:49:55 +0100388 * CTR definitions
389 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100390#define CTR_CWG_SHIFT U(24)
391#define CTR_CWG_MASK U(0xf)
392#define CTR_ERG_SHIFT U(20)
393#define CTR_ERG_MASK U(0xf)
394#define CTR_DMINLINE_SHIFT U(16)
395#define CTR_DMINLINE_WIDTH U(4)
396#define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
397#define CTR_L1IP_SHIFT U(14)
398#define CTR_L1IP_MASK U(0x3)
399#define CTR_IMINLINE_SHIFT U(0)
400#define CTR_IMINLINE_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100401
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100402#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Soby Mathewc6820d12016-05-09 17:49:55 +0100403
David Cunado5f55e282016-10-31 17:37:34 +0000404/* PMCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100405#define PMCR_N_SHIFT U(11)
406#define PMCR_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000407#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100408#define PMCR_LC_BIT (U(1) << 6)
409#define PMCR_DP_BIT (U(1) << 5)
David Cunado5f55e282016-10-31 17:37:34 +0000410
Soby Mathewc6820d12016-05-09 17:49:55 +0100411/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000412 * Definitions of register offsets, fields and macros for CPU system
413 * instructions.
414 ******************************************************************************/
415
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100416#define TLBI_ADDR_SHIFT U(0)
417#define TLBI_ADDR_MASK U(0xFFFFF000)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000418#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
419
420/*******************************************************************************
Soby Mathewc6820d12016-05-09 17:49:55 +0100421 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
422 * system level implementation of the Generic Timer.
423 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100424#define CNTCTLBASE_CNTFRQ U(0x0)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100425#define CNTNSAR U(0x4)
Soby Mathewc6820d12016-05-09 17:49:55 +0100426#define CNTNSAR_NS_SHIFT(x) (x)
427
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100428#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
429#define CNTACR_RPCT_SHIFT U(0x0)
430#define CNTACR_RVCT_SHIFT U(0x1)
431#define CNTACR_RFRQ_SHIFT U(0x2)
432#define CNTACR_RVOFF_SHIFT U(0x3)
433#define CNTACR_RWVT_SHIFT U(0x4)
434#define CNTACR_RWPT_SHIFT U(0x5)
Soby Mathewc6820d12016-05-09 17:49:55 +0100435
Soby Mathew2d9f7952018-06-11 16:21:30 +0100436/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000437 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100438 * system level implementation of the Generic Timer.
439 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000440/* Physical Count register. */
441#define CNTPCT_LO U(0x0)
442/* Counter Frequency register. */
443#define CNTBASEN_CNTFRQ U(0x10)
444/* Physical Timer CompareValue register. */
445#define CNTP_CVAL_LO U(0x20)
446/* Physical Timer Control register. */
447#define CNTP_CTL U(0x2c)
448
449/* Physical timer control register bit fields shifts and masks */
450#define CNTP_CTL_ENABLE_SHIFT 0
451#define CNTP_CTL_IMASK_SHIFT 1
452#define CNTP_CTL_ISTATUS_SHIFT 2
453
454#define CNTP_CTL_ENABLE_MASK U(1)
455#define CNTP_CTL_IMASK_MASK U(1)
456#define CNTP_CTL_ISTATUS_MASK U(1)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100457
Soby Mathewc6820d12016-05-09 17:49:55 +0100458/* MAIR macros */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000459#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
460#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
Soby Mathewc6820d12016-05-09 17:49:55 +0100461
462/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
463#define SCR p15, 0, c1, c1, 0
464#define SCTLR p15, 0, c1, c0, 0
Etienne Carriere70a004b2017-11-05 22:56:03 +0100465#define ACTLR p15, 0, c1, c0, 1
dp-arm595d0d52017-02-08 11:51:50 +0000466#define SDCR p15, 0, c1, c3, 1
Soby Mathewc6820d12016-05-09 17:49:55 +0100467#define MPIDR p15, 0, c0, c0, 5
468#define MIDR p15, 0, c0, c0, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000469#define HVBAR p15, 4, c12, c0, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100470#define VBAR p15, 0, c12, c0, 0
471#define MVBAR p15, 0, c12, c0, 1
472#define NSACR p15, 0, c1, c1, 2
473#define CPACR p15, 0, c1, c0, 2
474#define DCCIMVAC p15, 0, c7, c14, 1
475#define DCCMVAC p15, 0, c7, c10, 1
476#define DCIMVAC p15, 0, c7, c6, 1
477#define DCCISW p15, 0, c7, c14, 2
478#define DCCSW p15, 0, c7, c10, 2
479#define DCISW p15, 0, c7, c6, 2
480#define CTR p15, 0, c0, c0, 1
481#define CNTFRQ p15, 0, c14, c0, 0
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000482#define ID_MMFR4 p15, 0, c0, c2, 6
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100483#define ID_PFR0 p15, 0, c0, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100484#define ID_PFR1 p15, 0, c0, c1, 1
485#define MAIR0 p15, 0, c10, c2, 0
486#define MAIR1 p15, 0, c10, c2, 1
487#define TTBCR p15, 0, c2, c0, 2
488#define TTBR0 p15, 0, c2, c0, 0
489#define TTBR1 p15, 0, c2, c0, 1
490#define TLBIALL p15, 0, c8, c7, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000491#define TLBIALLH p15, 4, c8, c7, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100492#define TLBIALLIS p15, 0, c8, c3, 0
493#define TLBIMVA p15, 0, c8, c7, 1
494#define TLBIMVAA p15, 0, c8, c7, 3
Antonio Nino Diazac998032017-02-27 17:23:54 +0000495#define TLBIMVAAIS p15, 0, c8, c3, 3
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100496#define TLBIMVAHIS p15, 4, c8, c3, 1
Antonio Nino Diazac998032017-02-27 17:23:54 +0000497#define BPIALLIS p15, 0, c7, c1, 6
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000498#define BPIALL p15, 0, c7, c5, 6
499#define ICIALLU p15, 0, c7, c5, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100500#define HSCTLR p15, 4, c1, c0, 0
501#define HCR p15, 4, c1, c1, 0
502#define HCPTR p15, 4, c1, c1, 2
David Cunadofee86532017-04-13 22:38:29 +0100503#define HSTR p15, 4, c1, c1, 3
Soby Mathewc6820d12016-05-09 17:49:55 +0100504#define CNTHCTL p15, 4, c14, c1, 0
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000505#define CNTKCTL p15, 0, c14, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100506#define VPIDR p15, 4, c0, c0, 0
507#define VMPIDR p15, 4, c0, c0, 5
508#define ISR p15, 0, c12, c1, 0
509#define CLIDR p15, 1, c0, c0, 1
510#define CSSELR p15, 2, c0, c0, 0
511#define CCSIDR p15, 1, c0, c0, 0
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100512#define HTCR p15, 4, c2, c0, 2
513#define HMAIR0 p15, 4, c10, c2, 0
Douglas Raillard77414632018-08-21 12:54:45 +0100514#define ATS1CPR p15, 0, c7, c8, 0
515#define ATS1HR p15, 4, c7, c8, 0
Yatharth Kochara9f776c2016-11-10 16:17:51 +0000516#define DBGOSDLR p14, 0, c1, c3, 4
Soby Mathewc6820d12016-05-09 17:49:55 +0100517
David Cunado5f55e282016-10-31 17:37:34 +0000518/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
519#define HDCR p15, 4, c1, c1, 1
David Cunado5f55e282016-10-31 17:37:34 +0000520#define PMCR p15, 0, c9, c12, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000521#define CNTHP_TVAL p15, 4, c14, c2, 0
David Cunadoc14b08e2016-11-25 00:21:59 +0000522#define CNTHP_CTL p15, 4, c14, c2, 1
David Cunado5f55e282016-10-31 17:37:34 +0000523
Etienne Carriere70a004b2017-11-05 22:56:03 +0100524/* AArch32 coproc registers for 32bit MMU descriptor support */
525#define PRRR p15, 0, c10, c2, 0
526#define NMRR p15, 0, c10, c2, 1
527#define DACR p15, 0, c3, c0, 0
528
Soby Mathewc6820d12016-05-09 17:49:55 +0100529/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
530#define ICC_IAR1 p15, 0, c12, c12, 0
531#define ICC_IAR0 p15, 0, c12, c8, 0
532#define ICC_EOIR1 p15, 0, c12, c12, 1
533#define ICC_EOIR0 p15, 0, c12, c8, 1
534#define ICC_HPPIR1 p15, 0, c12, c12, 2
535#define ICC_HPPIR0 p15, 0, c12, c8, 2
536#define ICC_BPR1 p15, 0, c12, c12, 3
537#define ICC_BPR0 p15, 0, c12, c8, 3
538#define ICC_DIR p15, 0, c12, c11, 1
539#define ICC_PMR p15, 0, c4, c6, 0
540#define ICC_RPR p15, 0, c12, c11, 3
541#define ICC_CTLR p15, 0, c12, c12, 4
542#define ICC_MCTLR p15, 6, c12, c12, 4
543#define ICC_SRE p15, 0, c12, c12, 5
544#define ICC_HSRE p15, 4, c12, c9, 5
545#define ICC_MSRE p15, 6, c12, c12, 5
546#define ICC_IGRPEN0 p15, 0, c12, c12, 6
547#define ICC_IGRPEN1 p15, 0, c12, c12, 7
548#define ICC_MGRPEN1 p15, 6, c12, c12, 7
549
550/* 64 bit system register defines The format is: coproc, opt1, CRm */
551#define TTBR0_64 p15, 0, c2
552#define TTBR1_64 p15, 1, c2
553#define CNTVOFF_64 p15, 4, c14
554#define VTTBR_64 p15, 6, c2
555#define CNTPCT_64 p15, 0, c14
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100556#define HTTBR_64 p15, 4, c2
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000557#define CNTHP_CVAL_64 p15, 6, c14
Douglas Raillard77414632018-08-21 12:54:45 +0100558#define PAR_64 p15, 0, c7
Soby Mathewc6820d12016-05-09 17:49:55 +0100559
560/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
561#define ICC_SGI1R_EL1_64 p15, 0, c12
562#define ICC_ASGI1R_EL1_64 p15, 1, c12
563#define ICC_SGI0R_EL1_64 p15, 2, c12
564
Isla Mitchell02c63072017-07-21 14:44:36 +0100565/*******************************************************************************
566 * Definitions of MAIR encodings for device and normal memory
567 ******************************************************************************/
568/*
569 * MAIR encodings for device memory attributes.
570 */
571#define MAIR_DEV_nGnRnE U(0x0)
572#define MAIR_DEV_nGnRE U(0x4)
573#define MAIR_DEV_nGRE U(0x8)
574#define MAIR_DEV_GRE U(0xc)
575
576/*
577 * MAIR encodings for normal memory attributes.
578 *
579 * Cache Policy
580 * WT: Write Through
581 * WB: Write Back
582 * NC: Non-Cacheable
583 *
584 * Transient Hint
585 * NTR: Non-Transient
586 * TR: Transient
587 *
588 * Allocation Policy
589 * RA: Read Allocate
590 * WA: Write Allocate
591 * RWA: Read and Write Allocate
592 * NA: No Allocation
593 */
594#define MAIR_NORM_WT_TR_WA U(0x1)
595#define MAIR_NORM_WT_TR_RA U(0x2)
596#define MAIR_NORM_WT_TR_RWA U(0x3)
597#define MAIR_NORM_NC U(0x4)
598#define MAIR_NORM_WB_TR_WA U(0x5)
599#define MAIR_NORM_WB_TR_RA U(0x6)
600#define MAIR_NORM_WB_TR_RWA U(0x7)
601#define MAIR_NORM_WT_NTR_NA U(0x8)
602#define MAIR_NORM_WT_NTR_WA U(0x9)
603#define MAIR_NORM_WT_NTR_RA U(0xa)
604#define MAIR_NORM_WT_NTR_RWA U(0xb)
605#define MAIR_NORM_WB_NTR_NA U(0xc)
606#define MAIR_NORM_WB_NTR_WA U(0xd)
607#define MAIR_NORM_WB_NTR_RA U(0xe)
608#define MAIR_NORM_WB_NTR_RWA U(0xf)
609
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100610#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100611
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100612#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
613 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100614
Douglas Raillard77414632018-08-21 12:54:45 +0100615/* PAR fields */
616#define PAR_F_SHIFT U(0)
617#define PAR_F_MASK ULL(0x1)
618#define PAR_ADDR_SHIFT U(12)
Yann Gautier812c3252018-09-20 15:48:52 +0200619#define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
Douglas Raillard77414632018-08-21 12:54:45 +0100620
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100621/*******************************************************************************
622 * Definitions for system register interface to AMU for ARMv8.4 onwards
623 ******************************************************************************/
624#define AMCR p15, 0, c13, c2, 0
625#define AMCFGR p15, 0, c13, c2, 1
626#define AMCGCR p15, 0, c13, c2, 2
627#define AMUSERENR p15, 0, c13, c2, 3
628#define AMCNTENCLR0 p15, 0, c13, c2, 4
629#define AMCNTENSET0 p15, 0, c13, c2, 5
630#define AMCNTENCLR1 p15, 0, c13, c3, 0
Joel Hutton0dcdd8d2017-12-21 15:21:20 +0000631#define AMCNTENSET1 p15, 0, c13, c3, 1
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100632
633/* Activity Monitor Group 0 Event Counter Registers */
634#define AMEVCNTR00 p15, 0, c0
635#define AMEVCNTR01 p15, 1, c0
636#define AMEVCNTR02 p15, 2, c0
637#define AMEVCNTR03 p15, 3, c0
638
639/* Activity Monitor Group 0 Event Type Registers */
640#define AMEVTYPER00 p15, 0, c13, c6, 0
641#define AMEVTYPER01 p15, 0, c13, c6, 1
642#define AMEVTYPER02 p15, 0, c13, c6, 2
643#define AMEVTYPER03 p15, 0, c13, c6, 3
644
Joel Hutton2691bc62017-12-12 15:47:55 +0000645/* Activity Monitor Group 1 Event Counter Registers */
646#define AMEVCNTR10 p15, 0, c4
647#define AMEVCNTR11 p15, 1, c4
648#define AMEVCNTR12 p15, 2, c4
649#define AMEVCNTR13 p15, 3, c4
650#define AMEVCNTR14 p15, 4, c4
651#define AMEVCNTR15 p15, 5, c4
652#define AMEVCNTR16 p15, 6, c4
653#define AMEVCNTR17 p15, 7, c4
654#define AMEVCNTR18 p15, 0, c5
655#define AMEVCNTR19 p15, 1, c5
656#define AMEVCNTR1A p15, 2, c5
657#define AMEVCNTR1B p15, 3, c5
658#define AMEVCNTR1C p15, 4, c5
659#define AMEVCNTR1D p15, 5, c5
660#define AMEVCNTR1E p15, 6, c5
661#define AMEVCNTR1F p15, 7, c5
662
663/* Activity Monitor Group 1 Event Type Registers */
664#define AMEVTYPER10 p15, 0, c13, c14, 0
665#define AMEVTYPER11 p15, 0, c13, c14, 1
666#define AMEVTYPER12 p15, 0, c13, c14, 2
667#define AMEVTYPER13 p15, 0, c13, c14, 3
668#define AMEVTYPER14 p15, 0, c13, c14, 4
669#define AMEVTYPER15 p15, 0, c13, c14, 5
670#define AMEVTYPER16 p15, 0, c13, c14, 6
671#define AMEVTYPER17 p15, 0, c13, c14, 7
672#define AMEVTYPER18 p15, 0, c13, c15, 0
673#define AMEVTYPER19 p15, 0, c13, c15, 1
674#define AMEVTYPER1A p15, 0, c13, c15, 2
675#define AMEVTYPER1B p15, 0, c13, c15, 3
676#define AMEVTYPER1C p15, 0, c13, c15, 4
677#define AMEVTYPER1D p15, 0, c13, c15, 5
678#define AMEVTYPER1E p15, 0, c13, c15, 6
679#define AMEVTYPER1F p15, 0, c13, c15, 7
680
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000681#endif /* ARCH_H */