Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 1 | /* |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a77.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
| 17 | #error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 22 | #error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 23 | #endif |
| 24 | |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 25 | #if WORKAROUND_CVE_2022_23960 |
| 26 | wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 |
| 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 29 | workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412 |
| 30 | /* move cpu revision in again and compare against r0p0 */ |
| 31 | mov x0, x7 |
| 32 | mov x1, #CPU_REV(0, 0) |
| 33 | bl cpu_rev_var_ls |
laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 34 | cbz x0, 1f |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 35 | |
laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 36 | ldr x0, =0x0 |
| 37 | msr CORTEX_A77_CPUPSELR_EL3, x0 |
| 38 | ldr x0, =0x00E8400000 |
| 39 | msr CORTEX_A77_CPUPOR_EL3, x0 |
| 40 | ldr x0, =0x00FFE00000 |
| 41 | msr CORTEX_A77_CPUPMR_EL3, x0 |
| 42 | ldr x0, =0x4004003FF |
| 43 | msr CORTEX_A77_CPUPCR_EL3, x0 |
| 44 | ldr x0, =0x1 |
| 45 | msr CORTEX_A77_CPUPSELR_EL3, x0 |
| 46 | ldr x0, =0x00E8C00040 |
| 47 | msr CORTEX_A77_CPUPOR_EL3, x0 |
| 48 | ldr x0, =0x00FFE00040 |
| 49 | msr CORTEX_A77_CPUPMR_EL3, x0 |
| 50 | b 2f |
| 51 | 1: |
| 52 | ldr x0, =0x0 |
| 53 | msr CORTEX_A77_CPUPSELR_EL3, x0 |
| 54 | ldr x0, =0x00E8400000 |
| 55 | msr CORTEX_A77_CPUPOR_EL3, x0 |
| 56 | ldr x0, =0x00FF600000 |
| 57 | msr CORTEX_A77_CPUPMR_EL3, x0 |
| 58 | ldr x0, =0x00E8E00080 |
| 59 | msr CORTEX_A77_CPUPOR2_EL3, x0 |
| 60 | ldr x0, =0x00FFE000C0 |
| 61 | msr CORTEX_A77_CPUPMR2_EL3, x0 |
| 62 | 2: |
| 63 | ldr x0, =0x04004003FF |
| 64 | msr CORTEX_A77_CPUPCR_EL3, x0 |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 65 | workaround_reset_end cortex_a77, ERRATUM(1508412) |
laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 66 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 67 | check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0) |
laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 68 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 69 | workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578 |
Boyan Karatotev | 1776f42 | 2023-01-27 11:56:40 +0000 | [diff] [blame] | 70 | /* Set bit 2 in ACTLR2_EL1 */ |
| 71 | mrs x1, CORTEX_A77_ACTLR2_EL1 |
| 72 | orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2 |
| 73 | msr CORTEX_A77_ACTLR2_EL1, x1 |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 74 | workaround_reset_end cortex_a77, ERRATUM(1791578) |
Boyan Karatotev | 1776f42 | 2023-01-27 11:56:40 +0000 | [diff] [blame] | 75 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 76 | check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1) |
Boyan Karatotev | 1776f42 | 2023-01-27 11:56:40 +0000 | [diff] [blame] | 77 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 78 | workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714 |
Boyan Karatotev | 1776f42 | 2023-01-27 11:56:40 +0000 | [diff] [blame] | 79 | /* Disable allocation of splintered pages in the L2 TLB */ |
| 80 | mrs x1, CORTEX_A77_CPUECTLR_EL1 |
| 81 | orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53 |
| 82 | msr CORTEX_A77_CPUECTLR_EL1, x1 |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 83 | workaround_reset_end cortex_a77, ERRATUM(1800714) |
Boyan Karatotev | 1776f42 | 2023-01-27 11:56:40 +0000 | [diff] [blame] | 84 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 85 | check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1) |
Boyan Karatotev | 1776f42 | 2023-01-27 11:56:40 +0000 | [diff] [blame] | 86 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 87 | workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 |
johpow01 | a2fa12c | 2020-09-10 13:39:26 -0500 | [diff] [blame] | 88 | /* Set bit 8 in ECTLR_EL1 */ |
| 89 | mrs x1, CORTEX_A77_CPUECTLR_EL1 |
| 90 | orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 |
| 91 | msr CORTEX_A77_CPUECTLR_EL1, x1 |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 92 | workaround_reset_end cortex_a77, ERRATUM(1925769) |
johpow01 | a2fa12c | 2020-09-10 13:39:26 -0500 | [diff] [blame] | 93 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 94 | check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) |
johpow01 | a2fa12c | 2020-09-10 13:39:26 -0500 | [diff] [blame] | 95 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 96 | workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167 |
laurenw-arm | f5dbbef | 2021-03-23 13:09:35 -0500 | [diff] [blame] | 97 | ldr x0,=0x4 |
| 98 | msr CORTEX_A77_CPUPSELR_EL3,x0 |
| 99 | ldr x0,=0x10E3900002 |
| 100 | msr CORTEX_A77_CPUPOR_EL3,x0 |
| 101 | ldr x0,=0x10FFF00083 |
| 102 | msr CORTEX_A77_CPUPMR_EL3,x0 |
| 103 | ldr x0,=0x2001003FF |
| 104 | msr CORTEX_A77_CPUPCR_EL3,x0 |
| 105 | |
| 106 | ldr x0,=0x5 |
| 107 | msr CORTEX_A77_CPUPSELR_EL3,x0 |
| 108 | ldr x0,=0x10E3800082 |
| 109 | msr CORTEX_A77_CPUPOR_EL3,x0 |
| 110 | ldr x0,=0x10FFF00083 |
| 111 | msr CORTEX_A77_CPUPMR_EL3,x0 |
| 112 | ldr x0,=0x2001003FF |
| 113 | msr CORTEX_A77_CPUPCR_EL3,x0 |
| 114 | |
| 115 | ldr x0,=0x6 |
| 116 | msr CORTEX_A77_CPUPSELR_EL3,x0 |
| 117 | ldr x0,=0x10E3800200 |
| 118 | msr CORTEX_A77_CPUPOR_EL3,x0 |
| 119 | ldr x0,=0x10FFF003E0 |
| 120 | msr CORTEX_A77_CPUPMR_EL3,x0 |
| 121 | ldr x0,=0x2001003FF |
| 122 | msr CORTEX_A77_CPUPCR_EL3,x0 |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 123 | workaround_reset_end cortex_a77, ERRATUM(1946167) |
laurenw-arm | f5dbbef | 2021-03-23 13:09:35 -0500 | [diff] [blame] | 124 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 125 | check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1) |
laurenw-arm | f5dbbef | 2021-03-23 13:09:35 -0500 | [diff] [blame] | 126 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 127 | workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587 |
Bipin Ravi | 8e91662 | 2022-06-08 15:27:00 -0500 | [diff] [blame] | 128 | /* Set bit 0 in ACTLR2_EL1 */ |
| 129 | mrs x1, CORTEX_A77_ACTLR2_EL1 |
| 130 | orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0 |
| 131 | msr CORTEX_A77_ACTLR2_EL1, x1 |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 132 | workaround_reset_end cortex_a77, ERRATUM(2356587) |
Bipin Ravi | 8e91662 | 2022-06-08 15:27:00 -0500 | [diff] [blame] | 133 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 134 | check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1) |
Boyan Karatotev | aaf5d29 | 2022-11-01 11:22:12 +0000 | [diff] [blame] | 135 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 136 | workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 |
Boyan Karatotev | aaf5d29 | 2022-11-01 11:22:12 +0000 | [diff] [blame] | 137 | /* dsb before isb of power down sequence */ |
| 138 | dsb sy |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 139 | workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB |
johpow01 | eb14610 | 2021-05-03 13:37:13 -0500 | [diff] [blame] | 140 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 141 | check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1) |
Bipin Ravi | 8e91662 | 2022-06-08 15:27:00 -0500 | [diff] [blame] | 142 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 143 | workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 144 | #if IMAGE_BL31 |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 145 | /* |
| 146 | * The Cortex-A77 generic vectors are overridden to apply errata |
| 147 | * mitigation on exception entry from lower ELs. |
| 148 | */ |
| 149 | adr x0, wa_cve_vbar_cortex_a77 |
| 150 | msr vbar_el3, x0 |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 151 | #endif /* IMAGE_BL31 */ |
| 152 | workaround_reset_end cortex_a77, CVE(2022, 23960) |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 153 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 154 | check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Boyan Karatotev | e5cf16b | 2022-09-27 10:37:54 +0100 | [diff] [blame] | 155 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 156 | /* ------------------------------------------------- |
| 157 | * The CPU Ops reset function for Cortex-A77. Must follow AAPCS. |
| 158 | * ------------------------------------------------- |
| 159 | */ |
| 160 | cpu_reset_func_start cortex_a77 |
| 161 | cpu_reset_func_end cortex_a77 |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 162 | |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 163 | /* --------------------------------------------- |
| 164 | * HW will do the cache maintenance while powering down |
| 165 | * --------------------------------------------- |
| 166 | */ |
| 167 | func cortex_a77_core_pwr_dwn |
| 168 | /* --------------------------------------------- |
| 169 | * Enable CPU power down bit in power control register |
| 170 | * --------------------------------------------- |
| 171 | */ |
| 172 | mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 |
| 173 | orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 174 | msr CORTEX_A77_CPUPWRCTLR_EL1, x0 |
Boyan Karatotev | aaf5d29 | 2022-11-01 11:22:12 +0000 | [diff] [blame] | 175 | #if ERRATA_A77_2743100 |
| 176 | mov x15, x30 |
| 177 | bl cpu_get_rev_var |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 178 | bl erratum_cortex_a77_2743100_wa |
Boyan Karatotev | aaf5d29 | 2022-11-01 11:22:12 +0000 | [diff] [blame] | 179 | mov x30, x15 |
| 180 | #endif /* ERRATA_A77_2743100 */ |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 181 | isb |
| 182 | ret |
| 183 | endfunc cortex_a77_core_pwr_dwn |
| 184 | |
Boyan Karatotev | a44c342 | 2023-01-27 12:12:56 +0000 | [diff] [blame^] | 185 | errata_report_shim cortex_a77 |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 186 | /* --------------------------------------------- |
| 187 | * This function provides Cortex-A77 specific |
| 188 | * register information for crash reporting. |
| 189 | * It needs to return with x6 pointing to |
| 190 | * a list of register names in ascii and |
| 191 | * x8 - x15 having values of registers to be |
| 192 | * reported. |
| 193 | * --------------------------------------------- |
| 194 | */ |
| 195 | .section .rodata.cortex_a77_regs, "aS" |
| 196 | cortex_a77_regs: /* The ascii list of register names to be reported */ |
| 197 | .asciz "cpuectlr_el1", "" |
| 198 | |
| 199 | func cortex_a77_cpu_reg_dump |
| 200 | adr x6, cortex_a77_regs |
| 201 | mrs x8, CORTEX_A77_CPUECTLR_EL1 |
| 202 | ret |
| 203 | endfunc cortex_a77_cpu_reg_dump |
| 204 | |
| 205 | declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 206 | cortex_a77_reset_func, \ |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 207 | cortex_a77_core_pwr_dwn |