Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 1 | /* |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <assert.h> |
Varun Wadekar | 66ff012 | 2016-04-26 11:34:54 -0700 | [diff] [blame] | 32 | #include <bl_common.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 33 | #include <debug.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 34 | #include <platform_def.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 35 | #include <smmu.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 36 | #include <string.h> |
| 37 | #include <tegra_private.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 38 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 39 | /* SMMU IDs currently supported by the driver */ |
| 40 | enum { |
| 41 | TEGRA_SMMU0, |
| 42 | TEGRA_SMMU1, |
| 43 | TEGRA_SMMU2 |
| 44 | }; |
| 45 | |
| 46 | static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) |
| 47 | { |
| 48 | #if defined(TEGRA_SMMU0_BASE) |
| 49 | if (smmu_id == TEGRA_SMMU0) |
| 50 | return mmio_read_32(TEGRA_SMMU0_BASE + off); |
| 51 | #endif |
| 52 | |
| 53 | #if defined(TEGRA_SMMU1_BASE) |
| 54 | if (smmu_id == TEGRA_SMMU1) |
| 55 | return mmio_read_32(TEGRA_SMMU1_BASE + off); |
| 56 | #endif |
| 57 | |
| 58 | #if defined(TEGRA_SMMU2_BASE) |
| 59 | if (smmu_id == TEGRA_SMMU2) |
| 60 | return mmio_read_32(TEGRA_SMMU2_BASE + off); |
| 61 | #endif |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | static void tegra_smmu_write_32(uint32_t smmu_id, |
| 67 | uint32_t off, uint32_t val) |
| 68 | { |
| 69 | #if defined(TEGRA_SMMU0_BASE) |
| 70 | if (smmu_id == TEGRA_SMMU0) |
| 71 | mmio_write_32(TEGRA_SMMU0_BASE + off, val); |
| 72 | #endif |
| 73 | |
| 74 | #if defined(TEGRA_SMMU1_BASE) |
| 75 | if (smmu_id == TEGRA_SMMU1) |
| 76 | mmio_write_32(TEGRA_SMMU1_BASE + off, val); |
| 77 | #endif |
| 78 | |
| 79 | #if defined(TEGRA_SMMU2_BASE) |
| 80 | if (smmu_id == TEGRA_SMMU2) |
| 81 | mmio_write_32(TEGRA_SMMU2_BASE + off, val); |
| 82 | #endif |
| 83 | } |
| 84 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 85 | /* |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 86 | * Save SMMU settings before "System Suspend" to TZDRAM |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 87 | */ |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 88 | void tegra_smmu_save_context(uint64_t smmu_ctx_addr) |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 89 | { |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 90 | uint32_t i, num_entries = 0; |
Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 91 | smmu_regs_t *smmu_ctx_regs; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 92 | #if DEBUG |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 93 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 94 | uint64_t tzdram_base = params_from_bl2->tzdram_base; |
| 95 | uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 96 | uint32_t reg_id1, pgshift, cb_size; |
| 97 | |
| 98 | /* sanity check SMMU settings c*/ |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 99 | reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1)); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 100 | pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12; |
| 101 | cb_size = (2 << pgshift) * \ |
| 102 | (1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1)); |
| 103 | |
| 104 | assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE))); |
| 105 | #endif |
| 106 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 107 | assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end)); |
| 108 | |
Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 109 | /* get SMMU context table */ |
| 110 | smmu_ctx_regs = plat_get_smmu_ctx(); |
| 111 | assert(smmu_ctx_regs); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 112 | |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 113 | /* |
| 114 | * smmu_ctx_regs[0].val contains the size of the context table minus |
| 115 | * the last entry. Sanity check the table size before we start with |
| 116 | * the context save operation. |
| 117 | */ |
| 118 | while (smmu_ctx_regs[num_entries].val != 0xFFFFFFFFU) { |
| 119 | num_entries++; |
| 120 | } |
| 121 | |
| 122 | /* panic if the sizes do not match */ |
| 123 | if (num_entries != smmu_ctx_regs[0].val) |
| 124 | panic(); |
| 125 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 126 | /* save SMMU register values */ |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 127 | for (i = 1; i < num_entries; i++) |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 128 | smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg); |
| 129 | |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 130 | /* increment by 1 to take care of the last entry */ |
| 131 | num_entries++; |
| 132 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 133 | /* Save SMMU config settings */ |
| 134 | memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs, |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 135 | (sizeof(smmu_regs_t) * num_entries)); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 136 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 137 | /* save the SMMU table address */ |
| 138 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO, |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 139 | (uint32_t)smmu_ctx_addr); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 140 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI, |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 141 | (uint32_t)(smmu_ctx_addr >> 32)); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 142 | } |
| 143 | |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 144 | #define SMMU_NUM_CONTEXTS 64 |
| 145 | #define SMMU_CONTEXT_BANK_MAX_IDX 64 |
| 146 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 147 | /* |
| 148 | * Init SMMU during boot or "System Suspend" exit |
| 149 | */ |
| 150 | void tegra_smmu_init(void) |
| 151 | { |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 152 | uint32_t val, cb_idx, smmu_id, ctx_base; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 153 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 154 | for (smmu_id = 0; smmu_id < NUM_SMMU_DEVICES; smmu_id++) { |
| 155 | /* Program the SMMU pagesize and reset CACHE_LOCK bit */ |
| 156 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
| 157 | val |= SMMU_GSR0_PGSIZE_64K; |
| 158 | val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 159 | tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 160 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 161 | /* reset CACHE LOCK bit for NS Aux. Config. Register */ |
| 162 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
| 163 | val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 164 | tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 165 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 166 | /* disable TCU prefetch for all contexts */ |
| 167 | ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) |
| 168 | + SMMU_CBn_ACTLR; |
| 169 | for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) { |
| 170 | val = tegra_smmu_read_32(smmu_id, |
| 171 | ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx)); |
| 172 | val &= ~SMMU_CBn_ACTLR_CPRE_BIT; |
| 173 | tegra_smmu_write_32(smmu_id, ctx_base + |
| 174 | (SMMU_GSR0_PGSIZE_64K * cb_idx), val); |
| 175 | } |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 176 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 177 | /* set CACHE LOCK bit for NS Aux. Config. Register */ |
| 178 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
| 179 | val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 180 | tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 181 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 182 | /* set CACHE LOCK bit for S Aux. Config. Register */ |
| 183 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
| 184 | val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 185 | tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); |
| 186 | } |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 187 | } |