Nishanth Menon | 0192f89 | 2016-10-14 01:13:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __PLATFORM_DEF_H__ |
| 8 | #define __PLATFORM_DEF_H__ |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <board_def.h> |
| 12 | #include <common_def.h> |
| 13 | |
| 14 | /******************************************************************************* |
| 15 | * Generic platform constants |
| 16 | ******************************************************************************/ |
| 17 | |
| 18 | /* Size of cacheable stack */ |
| 19 | #if IMAGE_BL31 |
| 20 | #define PLATFORM_STACK_SIZE 0x800 |
| 21 | #else |
| 22 | #define PLATFORM_STACK_SIZE 0x1000 |
| 23 | #endif |
| 24 | |
Benjamin Fair | f807a34 | 2016-10-18 14:32:06 -0500 | [diff] [blame] | 25 | #define PLATFORM_SYSTEM_COUNT 1 |
| 26 | #define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ |
| 27 | K3_CLUSTER1_CORE_COUNT + \ |
| 28 | K3_CLUSTER2_CORE_COUNT + \ |
| 29 | K3_CLUSTER3_CORE_COUNT) |
| 30 | |
| 31 | #define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_MSMC_PORT != UNUSED) + \ |
| 32 | (K3_CLUSTER1_MSMC_PORT != UNUSED) + \ |
| 33 | (K3_CLUSTER2_MSMC_PORT != UNUSED) + \ |
| 34 | (K3_CLUSTER3_MSMC_PORT != UNUSED)) |
| 35 | |
| 36 | #define UNUSED -1 |
| 37 | |
| 38 | #if !defined(K3_CLUSTER1_CORE_COUNT) || !defined(K3_CLUSTER1_MSMC_PORT) |
| 39 | #define K3_CLUSTER1_CORE_COUNT 0 |
| 40 | #define K3_CLUSTER1_MSMC_PORT UNUSED |
| 41 | #endif |
| 42 | |
| 43 | #if !defined(K3_CLUSTER2_CORE_COUNT) || !defined(K3_CLUSTER2_MSMC_PORT) |
| 44 | #define K3_CLUSTER2_CORE_COUNT 0 |
| 45 | #define K3_CLUSTER2_MSMC_PORT UNUSED |
| 46 | #endif |
| 47 | |
| 48 | #if !defined(K3_CLUSTER3_CORE_COUNT) || !defined(K3_CLUSTER3_MSMC_PORT) |
| 49 | #define K3_CLUSTER3_CORE_COUNT 0 |
| 50 | #define K3_CLUSTER3_MSMC_PORT UNUSED |
| 51 | #endif |
| 52 | |
| 53 | #if K3_CLUSTER0_MSMC_PORT == UNUSED |
| 54 | #error "ARM cluster 0 must be used" |
| 55 | #endif |
| 56 | |
| 57 | #if ((K3_CLUSTER1_MSMC_PORT == UNUSED) && (K3_CLUSTER1_CORE_COUNT != 0)) || \ |
| 58 | ((K3_CLUSTER2_MSMC_PORT == UNUSED) && (K3_CLUSTER2_CORE_COUNT != 0)) || \ |
| 59 | ((K3_CLUSTER3_MSMC_PORT == UNUSED) && (K3_CLUSTER3_CORE_COUNT != 0)) |
| 60 | #error "Unused ports must have 0 ARM cores" |
| 61 | #endif |
| 62 | |
| 63 | #define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT |
| 64 | |
Nishanth Menon | 0192f89 | 2016-10-14 01:13:34 +0000 | [diff] [blame] | 65 | #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ |
| 66 | PLATFORM_CORE_COUNT) |
| 67 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * Memory layout constants |
| 71 | ******************************************************************************/ |
| 72 | |
| 73 | /* |
| 74 | * ARM-TF lives in SRAM, partition it here |
| 75 | */ |
| 76 | |
| 77 | #define SHARED_RAM_BASE BL31_LIMIT |
| 78 | #define SHARED_RAM_SIZE 0x00001000 |
| 79 | |
| 80 | /* |
| 81 | * BL3-1 specific defines. |
| 82 | * |
| 83 | * Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM. |
| 84 | */ |
| 85 | #define BL31_BASE SEC_SRAM_BASE |
| 86 | #define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) |
| 87 | #define BL31_LIMIT (BL31_BASE + BL31_SIZE) |
| 88 | #define BL31_PROGBITS_LIMIT BL31_LIMIT |
| 89 | |
| 90 | /* |
Nishanth Menon | 3ed1b28 | 2016-10-14 01:13:45 +0000 | [diff] [blame] | 91 | * Defines the maximum number of translation tables that are allocated by the |
| 92 | * translation table library code. To minimize the amount of runtime memory |
| 93 | * used, choose the smallest value needed to map the required virtual addresses |
| 94 | * for each BL stage. |
| 95 | */ |
| 96 | #define MAX_XLAT_TABLES 8 |
| 97 | |
| 98 | /* |
| 99 | * Defines the maximum number of regions that are allocated by the translation |
| 100 | * table library code. A region consists of physical base address, virtual base |
| 101 | * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as |
| 102 | * defined in the `mmap_region_t` structure. The platform defines the regions |
| 103 | * that should be mapped. Then, the translation table library will create the |
| 104 | * corresponding tables and descriptors at runtime. To minimize the amount of |
| 105 | * runtime memory used, choose the smallest value needed to register the |
| 106 | * required regions for each BL stage. |
| 107 | */ |
| 108 | #define MAX_MMAP_REGIONS 8 |
| 109 | |
| 110 | /* |
| 111 | * Defines the total size of the address space in bytes. For example, for a 32 |
| 112 | * bit address space, this value should be `(1ull << 32)`. |
| 113 | */ |
| 114 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) |
| 115 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) |
| 116 | |
| 117 | /* |
Nishanth Menon | 0192f89 | 2016-10-14 01:13:34 +0000 | [diff] [blame] | 118 | * Some data must be aligned on the biggest cache line size in the platform. |
| 119 | * This is known only to the platform as it might have a combination of |
| 120 | * integrated and external caches. |
| 121 | */ |
| 122 | #define CACHE_WRITEBACK_SHIFT 6 |
| 123 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 124 | |
Nishanth Menon | ce97604 | 2016-10-14 01:13:44 +0000 | [diff] [blame] | 125 | /* Platform default console definitions */ |
| 126 | #ifndef K3_USART_BASE_ADDRESS |
| 127 | #define K3_USART_BASE_ADDRESS 0x02800000 |
| 128 | #endif |
| 129 | |
| 130 | /* USART has a default size for address space */ |
| 131 | #define K3_USART_SIZE 0x1000 |
| 132 | |
| 133 | #ifndef K3_USART_CLK_SPEED |
| 134 | #define K3_USART_CLK_SPEED 48000000 |
| 135 | #endif |
| 136 | |
| 137 | #ifndef K3_USART_BAUD |
| 138 | #define K3_USART_BAUD 115200 |
| 139 | #endif |
| 140 | |
| 141 | /* Crash console defaults */ |
| 142 | #define CRASH_CONSOLE_BASE K3_USART_BASE_ADDRESS |
| 143 | #define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED |
| 144 | #define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD |
| 145 | |
Nishanth Menon | 1f0b51b | 2016-10-14 01:13:48 +0000 | [diff] [blame] | 146 | /* Timer frequency */ |
| 147 | #ifndef SYS_COUNTER_FREQ_IN_TICKS |
| 148 | #define SYS_COUNTER_FREQ_IN_TICKS 200000000 |
| 149 | #endif |
| 150 | |
Nishanth Menon | f97ad37 | 2016-10-14 01:13:49 +0000 | [diff] [blame] | 151 | /* Interrupt numbers */ |
| 152 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 153 | |
| 154 | #define ARM_IRQ_SEC_SGI_0 8 |
| 155 | #define ARM_IRQ_SEC_SGI_1 9 |
| 156 | #define ARM_IRQ_SEC_SGI_2 10 |
| 157 | #define ARM_IRQ_SEC_SGI_3 11 |
| 158 | #define ARM_IRQ_SEC_SGI_4 12 |
| 159 | #define ARM_IRQ_SEC_SGI_5 13 |
| 160 | #define ARM_IRQ_SEC_SGI_6 14 |
| 161 | #define ARM_IRQ_SEC_SGI_7 15 |
| 162 | |
| 163 | /* |
| 164 | * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 165 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 166 | * as Group 0 interrupts. |
| 167 | */ |
| 168 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 169 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 170 | GIC_INTR_CFG_LEVEL), \ |
| 171 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 172 | GIC_INTR_CFG_EDGE), \ |
| 173 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 174 | GIC_INTR_CFG_EDGE), \ |
| 175 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 176 | GIC_INTR_CFG_EDGE), \ |
| 177 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 178 | GIC_INTR_CFG_EDGE), \ |
| 179 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 180 | GIC_INTR_CFG_EDGE), \ |
| 181 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 182 | GIC_INTR_CFG_EDGE) |
| 183 | |
| 184 | #define PLAT_ARM_G0_IRQ_PROPS(grp) \ |
| 185 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 186 | GIC_INTR_CFG_EDGE), \ |
| 187 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 188 | GIC_INTR_CFG_EDGE) |
| 189 | |
| 190 | #define K3_GICD_BASE 0x01800000 |
| 191 | #define K3_GICD_SIZE 0x10000 |
| 192 | #define K3_GICR_BASE 0x01880000 |
| 193 | #define K3_GICR_SIZE 0x100000 |
| 194 | |
Nishanth Menon | 0192f89 | 2016-10-14 01:13:34 +0000 | [diff] [blame] | 195 | #endif /* __PLATFORM_DEF_H__ */ |