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Haojian Zhuang3846f142017-05-24 08:49:26 +08001/*
Haojian Zhuang3bd94382018-01-28 23:33:02 +08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang3846f142017-05-24 08:49:26 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Leo Yana515c3b2017-05-27 13:15:40 +08007#include <arch_helpers.h>
Haojian Zhuang3846f142017-05-24 08:49:26 +08008#include <arm_gic.h>
9#include <assert.h>
10#include <bl_common.h>
11#include <cci.h>
12#include <console.h>
13#include <debug.h>
14#include <errno.h>
15#include <gicv2.h>
16#include <hi6220.h>
Michael Brandlafdff3c2018-02-22 16:30:30 +010017#include <hikey_def.h>
Haojian Zhuang3846f142017-05-24 08:49:26 +080018#include <hisi_ipc.h>
19#include <hisi_pwrc.h>
Haojian Zhuangf82732b2017-10-18 19:52:20 +080020#include <mmio.h>
Haojian Zhuang3846f142017-05-24 08:49:26 +080021#include <platform_def.h>
22
Haojian Zhuang3846f142017-05-24 08:49:26 +080023#include "hikey_private.h"
24
25/*
26 * The next 2 constants identify the extents of the code & RO data region.
27 * These addresses are used by the MMU setup code and therefore they must be
28 * page-aligned. It is the responsibility of the linker script to ensure that
29 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
30 */
31#define BL31_RO_BASE (unsigned long)(&__RO_START__)
32#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
33
34/*
35 * The next 2 constants identify the extents of the coherent memory region.
36 * These addresses are used by the MMU setup code and therefore they must be
37 * page-aligned. It is the responsibility of the linker script to ensure that
38 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
39 * page-aligned addresses.
40 */
41#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
42#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
43
44static entry_point_info_t bl32_ep_info;
45static entry_point_info_t bl33_ep_info;
46
47/******************************************************************************
48 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
49 * interrupts.
50 *****************************************************************************/
51const unsigned int g0_interrupt_array[] = {
52 IRQ_SEC_PHY_TIMER,
53 IRQ_SEC_SGI_0
54};
55
56/*
57 * Ideally `arm_gic_data` structure definition should be a `const` but it is
58 * kept as modifiable for overwriting with different GICD and GICC base when
59 * running on FVP with VE memory map.
60 */
61gicv2_driver_data_t hikey_gic_data = {
62 .gicd_base = PLAT_ARM_GICD_BASE,
63 .gicc_base = PLAT_ARM_GICC_BASE,
64 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
65 .g0_interrupt_array = g0_interrupt_array,
66};
67
68static const int cci_map[] = {
69 CCI400_SL_IFACE3_CLUSTER_IX,
70 CCI400_SL_IFACE4_CLUSTER_IX
71};
72
Victor Chong7d787f52017-08-16 13:53:56 +090073entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
Haojian Zhuang3846f142017-05-24 08:49:26 +080074{
75 entry_point_info_t *next_image_info;
76
77 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
78
79 /* None of the images on this platform can have 0x0 as the entrypoint */
80 if (next_image_info->pc)
81 return next_image_info;
82 return NULL;
83}
84
Victor Chong2d9a42d2017-08-17 15:21:10 +090085void bl31_early_platform_setup(void *from_bl2,
86 void *plat_params_from_bl2)
Haojian Zhuang3846f142017-05-24 08:49:26 +080087{
88 /* Initialize the console to provide early debug support */
89 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
90
91 /* Initialize CCI driver */
92 cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));
Leo Yana515c3b2017-05-27 13:15:40 +080093 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
Haojian Zhuang3846f142017-05-24 08:49:26 +080094
Victor Chong2d9a42d2017-08-17 15:21:10 +090095 /*
96 * Check params passed from BL2 should not be NULL,
97 */
98 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
99 assert(params_from_bl2 != NULL);
100 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
101 assert(params_from_bl2->h.version >= VERSION_2);
102
103 bl_params_node_t *bl_params = params_from_bl2->head;
104
105 /*
106 * Copy BL33 and BL32 (if present), entry point information.
107 * They are stored in Secure RAM, in BL2's address space.
108 */
109 while (bl_params) {
110 if (bl_params->image_id == BL32_IMAGE_ID)
111 bl32_ep_info = *bl_params->ep_info;
112
113 if (bl_params->image_id == BL33_IMAGE_ID)
114 bl33_ep_info = *bl_params->ep_info;
115
116 bl_params = bl_params->next_params_info;
117 }
118
119 if (bl33_ep_info.pc == 0)
120 panic();
Haojian Zhuang3846f142017-05-24 08:49:26 +0800121}
122
123void bl31_plat_arch_setup(void)
124{
125 hikey_init_mmu_el3(BL31_BASE,
126 BL31_LIMIT - BL31_BASE,
127 BL31_RO_BASE,
128 BL31_RO_LIMIT,
129 BL31_COHERENT_RAM_BASE,
130 BL31_COHERENT_RAM_LIMIT);
131}
132
Haojian Zhuangf82732b2017-10-18 19:52:20 +0800133/* Initialize EDMAC controller with non-secure mode. */
134static void hikey_edma_init(void)
135{
136 int i;
137 uint32_t non_secure;
138
139 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
140 mmio_write_32(EDMAC_SEC_CTRL, non_secure);
141
142 for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) {
143 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
144 }
145}
146
Haojian Zhuang3846f142017-05-24 08:49:26 +0800147void bl31_platform_setup(void)
148{
149 /* Initialize the GIC driver, cpu and distributor interfaces */
150 gicv2_driver_init(&hikey_gic_data);
151 gicv2_distif_init();
152 gicv2_pcpu_distif_init();
153 gicv2_cpuif_enable();
154
Haojian Zhuangf82732b2017-10-18 19:52:20 +0800155 hikey_edma_init();
156
Haojian Zhuang3846f142017-05-24 08:49:26 +0800157 hisi_ipc_init();
158 hisi_pwrc_setup();
159}
160
161void bl31_plat_runtime_setup(void)
162{
163}