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Zelalem Aweke13dc8f12021-07-09 14:20:03 -05001/*
2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <errno.h>
9#include <string.h>
10
11#include <arch_helpers.h>
12#include <arch_features.h>
13#include <bl31/bl31.h>
14#include <common/debug.h>
15#include <common/runtime_svc.h>
16#include <context.h>
17#include <lib/el3_runtime/context_mgmt.h>
18#include <lib/el3_runtime/pubsub.h>
johpow019d134022021-06-16 17:57:28 -050019#include <lib/gpt_rme/gpt_rme.h>
Zelalem Aweke13dc8f12021-07-09 14:20:03 -050020
21#include <lib/spinlock.h>
22#include <lib/utils.h>
23#include <lib/xlat_tables/xlat_tables_v2.h>
24#include <plat/common/common_def.h>
25#include <plat/common/platform.h>
26#include <platform_def.h>
27#include <services/gtsi_svc.h>
28#include <services/rmi_svc.h>
29#include <services/rmmd_svc.h>
30#include <smccc_helpers.h>
31#include "rmmd_initial_context.h"
32#include "rmmd_private.h"
33
34/*******************************************************************************
35 * RMM context information.
36 ******************************************************************************/
37rmmd_rmm_context_t rmm_context[PLATFORM_CORE_COUNT];
38
39/*******************************************************************************
40 * RMM entry point information. Discovered on the primary core and reused
41 * on secondary cores.
42 ******************************************************************************/
43static entry_point_info_t *rmm_ep_info;
44
45/*******************************************************************************
46 * Static function declaration.
47 ******************************************************************************/
48static int32_t rmm_init(void);
49static uint64_t rmmd_smc_forward(uint32_t smc_fid, uint32_t src_sec_state,
50 uint32_t dst_sec_state, uint64_t x1,
51 uint64_t x2, uint64_t x3, uint64_t x4,
52 void *handle);
53
54/*******************************************************************************
55 * This function takes an RMM context pointer and performs a synchronous entry
56 * into it.
57 ******************************************************************************/
58uint64_t rmmd_rmm_sync_entry(rmmd_rmm_context_t *rmm_ctx)
59{
60 uint64_t rc;
61
62 assert(rmm_ctx != NULL);
63
64 cm_set_context(&(rmm_ctx->cpu_ctx), REALM);
65
66 /* Save the current el1/el2 context before loading realm context. */
67 cm_el1_sysregs_context_save(NON_SECURE);
68 cm_el2_sysregs_context_save(NON_SECURE);
69
70 /* Restore the realm context assigned above */
71 cm_el1_sysregs_context_restore(REALM);
72 cm_el2_sysregs_context_restore(REALM);
73 cm_set_next_eret_context(REALM);
74
75 /* Enter RMM */
76 rc = rmmd_rmm_enter(&rmm_ctx->c_rt_ctx);
77
78 /* Save realm context */
79 cm_el1_sysregs_context_save(REALM);
80 cm_el2_sysregs_context_save(REALM);
81
82 /* Restore the el1/el2 context again. */
83 cm_el1_sysregs_context_restore(NON_SECURE);
84 cm_el2_sysregs_context_restore(NON_SECURE);
85
86 return rc;
87}
88
89/*******************************************************************************
90 * This function returns to the place where rmmd_rmm_sync_entry() was
91 * called originally.
92 ******************************************************************************/
93__dead2 void rmmd_rmm_sync_exit(uint64_t rc)
94{
95 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()];
96
97 /* Get context of the RMM in use by this CPU. */
98 assert(cm_get_context(REALM) == &(ctx->cpu_ctx));
99
100 /*
101 * The RMMD must have initiated the original request through a
102 * synchronous entry into RMM. Jump back to the original C runtime
103 * context with the value of rc in x0;
104 */
105 rmmd_rmm_exit(ctx->c_rt_ctx, rc);
106
107 panic();
108}
109
110static void rmm_el2_context_init(el2_sysregs_t *regs)
111{
112 regs->ctx_regs[CTX_SPSR_EL2 >> 3] = REALM_SPSR_EL2;
113 regs->ctx_regs[CTX_SCTLR_EL2 >> 3] = SCTLR_EL2_RES1;
114}
115
116/*******************************************************************************
117 * Jump to the RMM for the first time.
118 ******************************************************************************/
119static int32_t rmm_init(void)
120{
121
122 uint64_t rc;
123
124 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()];
125
126 INFO("RMM init start.\n");
127 ctx->state = RMM_STATE_RESET;
128
129 /* Initialize RMM EL2 context. */
130 rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
131
132 rc = rmmd_rmm_sync_entry(ctx);
133 if (rc != 0ULL) {
134 ERROR("RMM initialisation failed 0x%llx\n", rc);
135 panic();
136 }
137
138 ctx->state = RMM_STATE_IDLE;
139 INFO("RMM init end.\n");
140
141 return 1;
142}
143
144/*******************************************************************************
145 * Load and read RMM manifest, setup RMM.
146 ******************************************************************************/
147int rmmd_setup(void)
148{
149 uint32_t ep_attr;
150 unsigned int linear_id = plat_my_core_pos();
151 rmmd_rmm_context_t *rmm_ctx = &rmm_context[linear_id];
152
153 /* Make sure RME is supported. */
154 assert(get_armv9_2_feat_rme_support() != 0U);
155
156 rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM);
157 if (rmm_ep_info == NULL) {
158 WARN("No RMM image provided by BL2 boot loader, Booting "
159 "device without RMM initialization. SMCs destined for "
160 "RMM will return SMC_UNK\n");
161 return -ENOENT;
162 }
163
164 /* Under no circumstances will this parameter be 0 */
165 assert(rmm_ep_info->pc == RMM_BASE);
166
167 /* Initialise an entrypoint to set up the CPU context */
168 ep_attr = EP_REALM;
169 if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0U) {
170 ep_attr |= EP_EE_BIG;
171 }
172
173 SET_PARAM_HEAD(rmm_ep_info, PARAM_EP, VERSION_1, ep_attr);
174 rmm_ep_info->spsr = SPSR_64(MODE_EL2,
175 MODE_SP_ELX,
176 DISABLE_ALL_EXCEPTIONS);
177
178 /* Initialise RMM context with this entry point information */
179 cm_setup_context(&rmm_ctx->cpu_ctx, rmm_ep_info);
180
181 INFO("RMM setup done.\n");
182
183 /* Register init function for deferred init. */
184 bl31_register_rmm_init(&rmm_init);
185
186 return 0;
187}
188
189/*******************************************************************************
190 * Forward SMC to the other security state
191 ******************************************************************************/
192static uint64_t rmmd_smc_forward(uint32_t smc_fid, uint32_t src_sec_state,
193 uint32_t dst_sec_state, uint64_t x1,
194 uint64_t x2, uint64_t x3, uint64_t x4,
195 void *handle)
196{
197 /* Save incoming security state */
198 cm_el1_sysregs_context_save(src_sec_state);
199 cm_el2_sysregs_context_save(src_sec_state);
200
201 /* Restore outgoing security state */
202 cm_el1_sysregs_context_restore(dst_sec_state);
203 cm_el2_sysregs_context_restore(dst_sec_state);
204 cm_set_next_eret_context(dst_sec_state);
205
206 SMC_RET8(cm_get_context(dst_sec_state), smc_fid, x1, x2, x3, x4,
207 SMC_GET_GP(handle, CTX_GPREG_X5),
208 SMC_GET_GP(handle, CTX_GPREG_X6),
209 SMC_GET_GP(handle, CTX_GPREG_X7));
210}
211
212/*******************************************************************************
213 * This function handles all SMCs in the range reserved for RMI. Each call is
214 * either forwarded to the other security state or handled by the RMM dispatcher
215 ******************************************************************************/
216uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
217 uint64_t x3, uint64_t x4, void *cookie,
218 void *handle, uint64_t flags)
219{
220 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()];
221 uint32_t src_sec_state;
222
223 /* Determine which security state this SMC originated from */
224 src_sec_state = caller_sec_state(flags);
225
226 /* RMI must not be invoked by the Secure world */
227 if (src_sec_state == SMC_FROM_SECURE) {
228 WARN("RMM: RMI invoked by secure world.\n");
229 SMC_RET1(handle, SMC_UNK);
230 }
231
232 /*
233 * Forward an RMI call from the Normal world to the Realm world as it
234 * is.
235 */
236 if (src_sec_state == SMC_FROM_NON_SECURE) {
237 VERBOSE("RMM: RMI call from non-secure world.\n");
238 return rmmd_smc_forward(smc_fid, NON_SECURE, REALM,
239 x1, x2, x3, x4, handle);
240 }
241
242 assert(src_sec_state == SMC_FROM_REALM);
243
244 switch (smc_fid) {
245 case RMI_RMM_REQ_COMPLETE:
246 if (ctx->state == RMM_STATE_RESET) {
247 VERBOSE("RMM: running rmmd_rmm_sync_exit\n");
248 rmmd_rmm_sync_exit(x1);
249 }
250
251 return rmmd_smc_forward(x1, REALM, NON_SECURE,
252 x2, x3, x4, 0, handle);
253
254 default:
255 WARN("RMM: Unsupported RMM call 0x%08x\n", smc_fid);
256 SMC_RET1(handle, SMC_UNK);
257 }
258}
259
260/*******************************************************************************
261 * This cpu has been turned on. Enter RMM to initialise R-EL2. Entry into RMM
262 * is done after initialising minimal architectural state that guarantees safe
263 * execution.
264 ******************************************************************************/
265static void *rmmd_cpu_on_finish_handler(const void *arg)
266{
267 int32_t rc;
268 uint32_t linear_id = plat_my_core_pos();
269 rmmd_rmm_context_t *ctx = &rmm_context[linear_id];
270
271 ctx->state = RMM_STATE_RESET;
272
273 /* Initialise RMM context with this entry point information */
274 cm_setup_context(&ctx->cpu_ctx, rmm_ep_info);
275
276 /* Initialize RMM EL2 context. */
277 rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
278
279 rc = rmmd_rmm_sync_entry(ctx);
280 if (rc != 0) {
281 ERROR("RMM initialisation failed (%d) on CPU%d\n", rc,
282 linear_id);
283 panic();
284 }
285
286 ctx->state = RMM_STATE_IDLE;
287 return NULL;
288}
289
290/* Subscribe to PSCI CPU on to initialize RMM on secondary */
291SUBSCRIBE_TO_EVENT(psci_cpu_on_finish, rmmd_cpu_on_finish_handler);
292
293static int gtsi_transition_granule(uint64_t pa,
294 unsigned int src_sec_state,
295 unsigned int target_pas)
296{
297 int ret;
298
johpow019d134022021-06-16 17:57:28 -0500299 ret = gpt_transition_pas(pa, PAGE_SIZE_4KB, src_sec_state, target_pas);
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500300
301 /* Convert TF-A error codes into GTSI error codes */
302 if (ret == -EINVAL) {
johpow019d134022021-06-16 17:57:28 -0500303 ERROR("[GTSI] Transition failed: invalid %s\n", "address");
304 ERROR(" PA: 0x%llx, SRC: %d, PAS: %d\n", pa,
305 src_sec_state, target_pas);
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500306 ret = GRAN_TRANS_RET_BAD_ADDR;
307 } else if (ret == -EPERM) {
johpow019d134022021-06-16 17:57:28 -0500308 ERROR("[GTSI] Transition failed: invalid %s\n", "caller/PAS");
309 ERROR(" PA: 0x%llx, SRC: %d, PAS: %d\n", pa,
310 src_sec_state, target_pas);
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500311 ret = GRAN_TRANS_RET_BAD_PAS;
312 }
313
314 return ret;
315}
316
317/*******************************************************************************
318 * This function handles all SMCs in the range reserved for GTF.
319 ******************************************************************************/
320uint64_t rmmd_gtsi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
321 uint64_t x3, uint64_t x4, void *cookie,
322 void *handle, uint64_t flags)
323{
324 uint32_t src_sec_state;
325
326 /* Determine which security state this SMC originated from */
327 src_sec_state = caller_sec_state(flags);
328
329 if (src_sec_state != SMC_FROM_REALM) {
330 WARN("RMM: GTF call originated from secure or normal world\n");
331 SMC_RET1(handle, SMC_UNK);
332 }
333
334 switch (smc_fid) {
335 case SMC_ASC_MARK_REALM:
336 SMC_RET1(handle, gtsi_transition_granule(x1, SMC_FROM_REALM,
johpow019d134022021-06-16 17:57:28 -0500337 GPT_GPI_REALM));
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500338 case SMC_ASC_MARK_NONSECURE:
339 SMC_RET1(handle, gtsi_transition_granule(x1, SMC_FROM_REALM,
johpow019d134022021-06-16 17:57:28 -0500340 GPT_GPI_NS));
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500341 default:
342 WARN("RMM: Unsupported GTF call 0x%08x\n", smc_fid);
343 SMC_RET1(handle, SMC_UNK);
344 }
345}