| Manoj Kumar | 9b4e3d7 | 2020-07-09 09:56:02 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef RAINIER_H |
| 8 | #define RAINIER_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /* RAINIER MIDR for revision 0 */ |
| Jagadeesh Ujja | 27569ff | 2020-10-07 19:51:46 +0530 | [diff] [blame] | 13 | #define RAINIER_MIDR U(0x3f0f4120) |
| Manoj Kumar | 9b4e3d7 | 2020-07-09 09:56:02 +0100 | [diff] [blame] | 14 | |
| 15 | /* Exception Syndrome register EC code for IC Trap */ |
| 16 | #define RAINIER_EC_IC_TRAP U(0x1f) |
| 17 | |
| 18 | /******************************************************************************* |
| 19 | * CPU Power Control register specific definitions. |
| 20 | ******************************************************************************/ |
| 21 | #define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 22 | |
| 23 | /* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */ |
| 24 | #define RAINIER_CORE_PWRDN_EN_MASK U(0x1) |
| 25 | |
| 26 | #define RAINIER_ACTLR_AMEN_BIT (U(1) << 4) |
| 27 | |
| 28 | #define RAINIER_AMU_NR_COUNTERS U(5) |
| 29 | #define RAINIER_AMU_GROUP0_MASK U(0x1f) |
| 30 | |
| 31 | /******************************************************************************* |
| 32 | * CPU Extended Control register specific definitions. |
| 33 | ******************************************************************************/ |
| 34 | #define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 35 | |
| 36 | #define RAINIER_WS_THR_L2_MASK (ULL(3) << 24) |
| 37 | #define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) |
| 38 | |
| 39 | /******************************************************************************* |
| 40 | * CPU Auxiliary Control register specific definitions. |
| 41 | ******************************************************************************/ |
| 42 | #define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 43 | |
| 44 | #define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) |
| 45 | #define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) |
| 46 | |
| 47 | #define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| 48 | |
| 49 | #define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) |
| 50 | #define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) |
| 51 | #define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) |
| 52 | #define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) |
| 53 | #define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) |
| 54 | #define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) |
| 55 | |
| 56 | #define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2 |
| 57 | |
| 58 | #define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) |
| 59 | |
| 60 | /* Instruction patching registers */ |
| 61 | #define CPUPSELR_EL3 S3_6_C15_C8_0 |
| 62 | #define CPUPCR_EL3 S3_6_C15_C8_1 |
| 63 | #define CPUPOR_EL3 S3_6_C15_C8_2 |
| 64 | #define CPUPMR_EL3 S3_6_C15_C8_3 |
| 65 | |
| 66 | #endif /* RAINIER_H */ |