| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
| Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | .macro func_prologue |
| 32 | stp x29, x30, [sp, #-0x10]! |
| 33 | mov x29,sp |
| 34 | .endm |
| 35 | |
| 36 | .macro func_epilogue |
| 37 | ldp x29, x30, [sp], #0x10 |
| 38 | .endm |
| 39 | |
| 40 | |
| 41 | .macro dcache_line_size reg, tmp |
| Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 42 | mrs \tmp, ctr_el0 |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 43 | ubfx \tmp, \tmp, #16, #4 |
| Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 44 | mov \reg, #4 |
| 45 | lsl \reg, \reg, \tmp |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 46 | .endm |
| 47 | |
| 48 | |
| 49 | .macro icache_line_size reg, tmp |
| Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 50 | mrs \tmp, ctr_el0 |
| 51 | and \tmp, \tmp, #0xf |
| 52 | mov \reg, #4 |
| 53 | lsl \reg, \reg, \tmp |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 54 | .endm |
| 55 | |
| 56 | |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 57 | .macro smc_check label |
| 58 | bl read_esr |
| 59 | ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 60 | cmp x0, #EC_AARCH64_SMC |
| 61 | b.ne $label |
| 62 | .endm |
| 63 | |
| 64 | |
| 65 | .macro setup_dcsw_op_args start_level, end_level, clidr, shift, fw, ls |
| 66 | mrs \clidr, clidr_el1 |
| 67 | mov \start_level, xzr |
| 68 | ubfx \end_level, \clidr, \shift, \fw |
| 69 | lsl \end_level, \end_level, \ls |
| 70 | .endm |
| Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 71 | |
| 72 | /* |
| 73 | * This macro verifies that the a given vector doesn't exceed the |
| 74 | * architectural limit of 32 instructions. This is meant to be placed |
| 75 | * immedately after the last instruction in the vector. It takes the |
| 76 | * vector entry as the parameter |
| 77 | */ |
| 78 | .macro check_vector_size since |
| 79 | .if (. - \since) > (32 * 4) |
| 80 | .error "Vector exceeds 32 instructions" |
| 81 | .endif |
| 82 | .endm |