| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 1 | /* |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A76_H |
| 8 | #define CORTEX_A76_H |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 9 | |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 12 | /* Cortex-A76 MIDR for revision 0 */ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 13 | #define CORTEX_A76_MIDR U(0x410fd0b0) |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 19 | #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 20 | |
| Dimitris Papastamos | 312e17e | 2018-05-16 09:59:54 +0100 | [diff] [blame] | 21 | /******************************************************************************* |
| 22 | * CPU Auxiliary Control register specific definitions. |
| 23 | ******************************************************************************/ |
| 24 | #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| 25 | |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 26 | #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) |
| Dimitris Papastamos | 312e17e | 2018-05-16 09:59:54 +0100 | [diff] [blame] | 27 | |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 28 | /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 29 | #define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 30 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 31 | #endif /* CORTEX_A76_H */ |