blob: dbf5941e308cf2f464eab5a68952c13b7b5132b3 [file] [log] [blame]
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +01001/*
Bipin Ravi86499742022-01-18 01:59:06 -06002 * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <cpu_macros.S>
10#include <neoverse_n2.h>
Bipin Ravi86499742022-01-18 01:59:06 -060011#include "wa_cve_2022_23960_bhb_vector.S"
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010012
13/* Hardware handled coherency */
14#if HW_ASSISTED_COHERENCY == 0
15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled"
16#endif
17
18/* 64-bit only core */
19#if CTX_INCLUDE_AARCH32_REGS == 1
20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
21#endif
22
Bipin Ravi86499742022-01-18 01:59:06 -060023#if WORKAROUND_CVE_2022_23960
24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
25#endif /* WORKAROUND_CVE_2022_23960 */
26
nayanpatel-arm277581e2021-08-06 17:46:10 -070027/* --------------------------------------------------
28 * Errata Workaround for Neoverse N2 Erratum 2002655.
29 * This applies to revision r0p0 of Neoverse N2. it is still open.
30 * Inputs:
31 * x0: variant[4:7] and revision[0:3] of current cpu.
32 * Shall clobber: x0-x17
33 * --------------------------------------------------
34 */
35func errata_n2_2002655_wa
36 /* Check revision. */
37 mov x17, x30
38 bl check_errata_2002655
39 cbz x0, 1f
40
41 /* Apply instruction patching sequence */
42 ldr x0,=0x6
43 msr S3_6_c15_c8_0,x0
44 ldr x0,=0xF3A08002
45 msr S3_6_c15_c8_2,x0
46 ldr x0,=0xFFF0F7FE
47 msr S3_6_c15_c8_3,x0
48 ldr x0,=0x40000001003ff
49 msr S3_6_c15_c8_1,x0
50 ldr x0,=0x7
51 msr S3_6_c15_c8_0,x0
52 ldr x0,=0xBF200000
53 msr S3_6_c15_c8_2,x0
54 ldr x0,=0xFFEF0000
55 msr S3_6_c15_c8_3,x0
56 ldr x0,=0x40000001003f3
57 msr S3_6_c15_c8_1,x0
58 isb
591:
60 ret x17
61endfunc errata_n2_2002655_wa
62
63func check_errata_2002655
64 /* Applies to r0p0 */
65 mov x1, #0x00
66 b cpu_rev_var_ls
67endfunc check_errata_2002655
68
Bipin Ravieb35e852021-03-30 16:08:32 -050069/* ---------------------------------------------------------------
70 * Errata Workaround for Neoverse N2 Erratum 2067956.
71 * This applies to revision r0p0 of Neoverse N2 and is still open.
72 * Inputs:
73 * x0: variant[4:7] and revision[0:3] of current cpu.
74 * Shall clobber: x0-x17
75 * ---------------------------------------------------------------
76 */
77func errata_n2_2067956_wa
78 /* Compare x0 against revision r0p0 */
79 mov x17, x30
80 bl check_errata_2067956
81 cbz x0, 1f
82 mrs x1, NEOVERSE_N2_CPUACTLR_EL1
83 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
84 msr NEOVERSE_N2_CPUACTLR_EL1, x1
851:
86 ret x17
87endfunc errata_n2_2067956_wa
88
89func check_errata_2067956
90 /* Applies to r0p0 */
91 mov x1, #0x00
92 b cpu_rev_var_ls
93endfunc check_errata_2067956
94
Bipin Ravi7f565472021-03-31 10:10:27 -050095/* ---------------------------------------------------------------
96 * Errata Workaround for Neoverse N2 Erratum 2025414.
97 * This applies to revision r0p0 of Neoverse N2 and is still open.
98 * Inputs:
99 * x0: variant[4:7] and revision[0:3] of current cpu.
100 * Shall clobber: x0-x17
101 * ---------------------------------------------------------------
102 */
103func errata_n2_2025414_wa
104 /* Compare x0 against revision r0p0 */
105 mov x17, x30
106 bl check_errata_2025414
107 cbz x0, 1f
108 mrs x1, NEOVERSE_N2_CPUECTLR_EL1
109 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
110 msr NEOVERSE_N2_CPUECTLR_EL1, x1
111
1121:
113 ret x17
114endfunc errata_n2_2025414_wa
115
116func check_errata_2025414
117 /* Applies to r0p0 */
118 mov x1, #0x00
119 b cpu_rev_var_ls
120endfunc check_errata_2025414
121
Bipin Ravi7e030692021-08-30 13:02:51 -0500122/* ---------------------------------------------------------------
123 * Errata Workaround for Neoverse N2 Erratum 2189731.
124 * This applies to revision r0p0 of Neoverse N2 and is still open.
125 * Inputs:
126 * x0: variant[4:7] and revision[0:3] of current cpu.
127 * Shall clobber: x0-x17
128 * ---------------------------------------------------------------
129 */
130func errata_n2_2189731_wa
131 /* Compare x0 against revision r0p0 */
132 mov x17, x30
133 bl check_errata_2189731
134 cbz x0, 1f
135 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
136 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
137 msr NEOVERSE_N2_CPUACTLR5_EL1, x1
138
1391:
140 ret x17
141endfunc errata_n2_2189731_wa
142
143func check_errata_2189731
144 /* Applies to r0p0 */
145 mov x1, #0x00
146 b cpu_rev_var_ls
147endfunc check_errata_2189731
148
Bipin Ravi0ba631c2021-09-01 01:36:43 -0500149/* --------------------------------------------------
150 * Errata Workaround for Neoverse N2 Erratum 2138956.
151 * This applies to revision r0p0 of Neoverse N2. it is still open.
152 * Inputs:
153 * x0: variant[4:7] and revision[0:3] of current cpu.
154 * Shall clobber: x0-x17
155 * --------------------------------------------------
156 */
157func errata_n2_2138956_wa
158 /* Check revision. */
159 mov x17, x30
160 bl check_errata_2138956
161 cbz x0, 1f
162
163 /* Apply instruction patching sequence */
164 ldr x0,=0x3
165 msr S3_6_c15_c8_0,x0
166 ldr x0,=0xF3A08002
167 msr S3_6_c15_c8_2,x0
168 ldr x0,=0xFFF0F7FE
169 msr S3_6_c15_c8_3,x0
170 ldr x0,=0x10002001003FF
171 msr S3_6_c15_c8_1,x0
172 ldr x0,=0x4
173 msr S3_6_c15_c8_0,x0
174 ldr x0,=0xBF200000
175 msr S3_6_c15_c8_2,x0
176 ldr x0,=0xFFEF0000
177 msr S3_6_c15_c8_3,x0
178 ldr x0,=0x10002001003F3
179 msr S3_6_c15_c8_1,x0
180 isb
1811:
182 ret x17
183endfunc errata_n2_2138956_wa
184
185func check_errata_2138956
186 /* Applies to r0p0 */
187 mov x1, #0x00
188 b cpu_rev_var_ls
189endfunc check_errata_2138956
190
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -0700191/* --------------------------------------------------
nayanpatel-arm2f153992021-10-06 15:31:24 -0700192 * Errata Workaround for Neoverse N2 Erratum 2242415.
193 * This applies to revision r0p0 of Neoverse N2. it is still open.
194 * Inputs:
195 * x0: variant[4:7] and revision[0:3] of current cpu.
196 * Shall clobber: x0-x1, x17
197 * --------------------------------------------------
198 */
199func errata_n2_2242415_wa
200 /* Check revision. */
201 mov x17, x30
202 bl check_errata_2242415
203 cbz x0, 1f
204
205 /* Apply instruction patching sequence */
206 mrs x1, NEOVERSE_N2_CPUACTLR_EL1
207 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
208 msr NEOVERSE_N2_CPUACTLR_EL1, x1
2091:
210 ret x17
211endfunc errata_n2_2242415_wa
212
213func check_errata_2242415
214 /* Applies to r0p0 */
215 mov x1, #0x00
216 b cpu_rev_var_ls
217endfunc check_errata_2242415
218
219/* --------------------------------------------------
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -0700220 * Errata Workaround for Neoverse N2 Erratum 2138953.
221 * This applies to revision r0p0 of Neoverse N2. it is still open.
222 * Inputs:
223 * x0: variant[4:7] and revision[0:3] of current cpu.
224 * Shall clobber: x0-x1, x17
225 * --------------------------------------------------
226 */
227func errata_n2_2138953_wa
228 /* Check revision. */
229 mov x17, x30
230 bl check_errata_2138953
231 cbz x0, 1f
232
233 /* Apply instruction patching sequence */
234 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
235 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
236 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
237 msr NEOVERSE_N2_CPUECTLR2_EL1, x1
2381:
239 ret x17
240endfunc errata_n2_2138953_wa
241
242func check_errata_2138953
243 /* Applies to r0p0 */
244 mov x1, #0x00
245 b cpu_rev_var_ls
246endfunc check_errata_2138953
247
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700248/* --------------------------------------------------
249 * Errata Workaround for Neoverse N2 Erratum 2138958.
250 * This applies to revision r0p0 of Neoverse N2. it is still open.
251 * Inputs:
252 * x0: variant[4:7] and revision[0:3] of current cpu.
253 * Shall clobber: x0-x1, x17
254 * --------------------------------------------------
255 */
256func errata_n2_2138958_wa
257 /* Check revision. */
258 mov x17, x30
259 bl check_errata_2138958
260 cbz x0, 1f
261
262 /* Apply instruction patching sequence */
263 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
264 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
265 msr NEOVERSE_N2_CPUACTLR5_EL1, x1
2661:
267 ret x17
268endfunc errata_n2_2138958_wa
269
270func check_errata_2138958
271 /* Applies to r0p0 */
272 mov x1, #0x00
273 b cpu_rev_var_ls
274endfunc check_errata_2138958
275
nayanpatel-armfed98132021-10-07 17:59:33 -0700276/* --------------------------------------------------
277 * Errata Workaround for Neoverse N2 Erratum 2242400.
278 * This applies to revision r0p0 of Neoverse N2. it is still open.
279 * Inputs:
280 * x0: variant[4:7] and revision[0:3] of current cpu.
281 * Shall clobber: x0-x1, x17
282 * --------------------------------------------------
283 */
284func errata_n2_2242400_wa
285 /* Check revision. */
286 mov x17, x30
287 bl check_errata_2242400
288 cbz x0, 1f
289
290 /* Apply instruction patching sequence */
291 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
292 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
293 msr NEOVERSE_N2_CPUACTLR5_EL1, x1
294 ldr x0, =0x2
295 msr S3_6_c15_c8_0, x0
296 ldr x0, =0x10F600E000
297 msr S3_6_c15_c8_2, x0
298 ldr x0, =0x10FF80E000
299 msr S3_6_c15_c8_3, x0
300 ldr x0, =0x80000000003FF
301 msr S3_6_c15_c8_1, x0
302 isb
3031:
304 ret x17
305endfunc errata_n2_2242400_wa
306
307func check_errata_2242400
308 /* Applies to r0p0 */
309 mov x1, #0x00
310 b cpu_rev_var_ls
311endfunc check_errata_2242400
312
nayanpatel-arm45b9f6f2021-10-20 17:30:46 -0700313/* --------------------------------------------------
314 * Errata Workaround for Neoverse N2 Erratum 2280757.
315 * This applies to revision r0p0 of Neoverse N2. it is still open.
316 * Inputs:
317 * x0: variant[4:7] and revision[0:3] of current cpu.
318 * Shall clobber: x0-x1, x17
319 * --------------------------------------------------
320 */
321func errata_n2_2280757_wa
322 /* Check revision. */
323 mov x17, x30
324 bl check_errata_2280757
325 cbz x0, 1f
326
327 /* Apply instruction patching sequence */
328 mrs x1, NEOVERSE_N2_CPUACTLR_EL1
329 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
330 msr NEOVERSE_N2_CPUACTLR_EL1, x1
3311:
332 ret x17
333endfunc errata_n2_2280757_wa
334
335func check_errata_2280757
336 /* Applies to r0p0 */
337 mov x1, #0x00
338 b cpu_rev_var_ls
339endfunc check_errata_2280757
340
Boyan Karatotevd3f8b4d2022-10-03 14:07:08 +0100341/* --------------------------------------------------
342 * Errata Workaround for Neoverse N2 Erratum 2326639.
343 * This applies to revision r0p0 of Neoverse N2,
344 * fixed in r0p1.
345 * Inputs:
346 * x0: variant[4:7] and revision[0:3] of current cpu.
347 * Shall clobber: x0-x1, x17
348 * --------------------------------------------------
349 */
350func errata_n2_2326639_wa
351 /* Check revision. */
352 mov x17, x30
353 bl check_errata_2326639
354 cbz x0, 1f
355
356 /* Set bit 36 in ACTLR2_EL1 */
357 mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
358 orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
359 msr NEOVERSE_N2_CPUACTLR2_EL1, x1
3601:
361 ret x17
362endfunc errata_n2_2326639_wa
363
364func check_errata_2326639
365 /* Applies to r0p0, fixed in r0p1 */
366 mov x1, #0x00
367 b cpu_rev_var_ls
368endfunc check_errata_2326639
Akram Ahmadb621bda2022-07-18 12:27:29 +0100369
370/* --------------------------------------------------
371 * Errata Workaround for Neoverse N2 Erratum 2376738.
372 * This applies to revision r0p0 of Neoverse N2,
373 * fixed in r0p1.
374 * Inputs:
375 * x0: variant[4:7] and revision[0:3] of current CPU.
376 * Shall clobber: x0-x1, x17
377 * --------------------------------------------------
378 */
379func errata_n2_2376738_wa
380 mov x17, x30
381 bl check_errata_2376738
382 cbz x0, 1f
383
384 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM
385 * ST to behave like PLD/PFRM LD and not cause
386 * invalidations to other PE caches.
387 */
388 mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
389 orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
390 msr NEOVERSE_N2_CPUACTLR2_EL1, x1
3911:
392 ret x17
393endfunc errata_n2_2376738_wa
394
395func check_errata_2376738
396 /* Applies to r0p0, fixed in r0p1 */
397 mov x1, 0x00
398 b cpu_rev_var_ls
399endfunc check_errata_2376738
400
Daniel Boulby1af2b112022-07-06 14:33:13 +0100401/* --------------------------------------------------
402 * Errata Workaround for Neoverse N2 Erratum 2388450.
403 * This applies to revision r0p0 of Neoverse N2,
404 * fixed in r0p1.
405 * Inputs:
406 * x0: variant[4:7] and revision[0:3] of current cpu.
407 * Shall clobber: x0-x1, x17
408 * --------------------------------------------------
409 */
410func errata_n2_2388450_wa
411 /* Check revision. */
412 mov x17, x30
413 bl check_errata_2388450
414 cbz x0, 1f
415
416 /*Set bit 40 in ACTLR2_EL1 */
417 mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
418 orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
419 msr NEOVERSE_N2_CPUACTLR2_EL1, x1
420 isb
4211:
422 ret x17
423endfunc errata_n2_2388450_wa
424
425func check_errata_2388450
426 /* Applies to r0p0, fixed in r0p1 */
427 mov x1, #0x00
428 b cpu_rev_var_ls
429endfunc check_errata_2388450
430
Bipin Ravicc744bf2022-12-07 17:01:26 -0600431/* -------------------------------------------------------
432 * Errata Workaround for Neoverse N2 Erratum 2743089.
433 * This applies to revisions <= r0p2 and is fixed in r0p3.
434 * x0: variant[4:7] and revision[0:3] of current cpu.
435 * Shall clobber: x0-x17
436 * -------------------------------------------------------
437 */
438func errata_n2_2743089_wa
439 mov x17, x30
440 bl check_errata_2743089
441 cbz x0, 1f
442
443 /* dsb before isb of power down sequence */
444 dsb sy
4451:
446 ret x17
447endfunc errata_n2_2743089_wa
448
449func check_errata_2743089
450 /* Applies to all revisions <= r0p2 */
451 mov x1, #0x02
452 b cpu_rev_var_ls
453endfunc check_errata_2743089
454
Bipin Ravi86499742022-01-18 01:59:06 -0600455func check_errata_cve_2022_23960
456#if WORKAROUND_CVE_2022_23960
457 mov x0, #ERRATA_APPLIES
458#else
459 mov x0, #ERRATA_MISSING
460#endif
461 ret
462endfunc check_errata_cve_2022_23960
463
Bipin Ravi7f565472021-03-31 10:10:27 -0500464 /* -------------------------------------------
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100465 * The CPU Ops reset function for Neoverse N2.
Bipin Ravi7f565472021-03-31 10:10:27 -0500466 * -------------------------------------------
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100467 */
468func neoverse_n2_reset_func
nayanpatel-arm277581e2021-08-06 17:46:10 -0700469 mov x19, x30
470
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100471 /* Check if the PE implements SSBS */
472 mrs x0, id_aa64pfr1_el1
473 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
474 b.eq 1f
475
476 /* Disable speculative loads */
477 msr SSBS, xzr
4781:
479 /* Force all cacheable atomic instructions to be near */
480 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1
481 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
482 msr NEOVERSE_N2_CPUACTLR2_EL1, x0
483
Bipin Ravi3f4cd572022-10-19 10:29:16 -0500484 /* Get the CPU revision and stash it in x18. */
485 bl cpu_get_rev_var
486 mov x18, x0
487
Bipin Raviaf40d692021-12-22 14:35:21 -0600488#if ERRATA_DSU_2313941
489 bl errata_dsu_2313941_wa
490#endif
491
Bipin Ravieb35e852021-03-30 16:08:32 -0500492#if ERRATA_N2_2067956
493 mov x0, x18
494 bl errata_n2_2067956_wa
495#endif
496
Bipin Ravi7f565472021-03-31 10:10:27 -0500497#if ERRATA_N2_2025414
nayanpatel-armfed98132021-10-07 17:59:33 -0700498 mov x0, x18
499 bl errata_n2_2025414_wa
Bipin Ravi7f565472021-03-31 10:10:27 -0500500#endif
501
Bipin Ravi7e030692021-08-30 13:02:51 -0500502#if ERRATA_N2_2189731
nayanpatel-armfed98132021-10-07 17:59:33 -0700503 mov x0, x18
504 bl errata_n2_2189731_wa
Bipin Ravi7e030692021-08-30 13:02:51 -0500505#endif
506
Bipin Ravi0ba631c2021-09-01 01:36:43 -0500507
508#if ERRATA_N2_2138956
509 mov x0, x18
510 bl errata_n2_2138956_wa
511#endif
512
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -0700513#if ERRATA_N2_2138953
514 mov x0, x18
515 bl errata_n2_2138953_wa
516#endif
517
nayanpatel-arm2f153992021-10-06 15:31:24 -0700518#if ERRATA_N2_2242415
519 mov x0, x18
520 bl errata_n2_2242415_wa
521#endif
522
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700523#if ERRATA_N2_2138958
524 mov x0, x18
525 bl errata_n2_2138958_wa
526#endif
527
nayanpatel-armfed98132021-10-07 17:59:33 -0700528#if ERRATA_N2_2242400
529 mov x0, x18
530 bl errata_n2_2242400_wa
531#endif
532
nayanpatel-arm45b9f6f2021-10-20 17:30:46 -0700533#if ERRATA_N2_2280757
534 mov x0, x18
535 bl errata_n2_2280757_wa
536#endif
537
Akram Ahmadb621bda2022-07-18 12:27:29 +0100538#if ERRATA_N2_2376738
539 mov x0, x18
540 bl errata_n2_2376738_wa
541#endif
542
Daniel Boulby1af2b112022-07-06 14:33:13 +0100543#if ERRATA_N2_2388450
544 mov x0, x18
545 bl errata_n2_2388450_wa
546#endif
547
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100548#if ENABLE_AMU
549 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
550 mrs x0, cptr_el3
551 orr x0, x0, #TAM_BIT
552 msr cptr_el3, x0
553
554 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
555 mrs x0, cptr_el2
556 orr x0, x0, #TAM_BIT
557 msr cptr_el2, x0
558
559 /* No need to enable the counters as this would be done at el3 exit */
560#endif
561
562#if NEOVERSE_Nx_EXTERNAL_LLC
563 /* Some systems may have External LLC, core needs to be made aware */
Bipin Ravieb35e852021-03-30 16:08:32 -0500564 mrs x0, NEOVERSE_N2_CPUECTLR_EL1
565 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
566 msr NEOVERSE_N2_CPUECTLR_EL1, x0
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100567#endif
568
nayanpatel-arm277581e2021-08-06 17:46:10 -0700569#if ERRATA_N2_2002655
570 mov x0, x18
571 bl errata_n2_2002655_wa
572#endif
573
Bipin Ravi86499742022-01-18 01:59:06 -0600574#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
575 /*
576 * The Neoverse-N2 generic vectors are overridden to apply errata
577 * mitigation on exception entry from lower ELs.
578 */
579 adr x0, wa_cve_vbar_neoverse_n2
580 msr vbar_el3, x0
581#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
582
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100583 isb
Bipin Ravieb35e852021-03-30 16:08:32 -0500584 ret x19
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100585endfunc neoverse_n2_reset_func
586
587func neoverse_n2_core_pwr_dwn
Boyan Karatotevd3f8b4d2022-10-03 14:07:08 +0100588#if ERRATA_N2_2326639
589 mov x15, x30
590 bl cpu_get_rev_var
591 bl errata_n2_2326639_wa
592 mov x30, x15
593#endif /* ERRATA_N2_2326639 */
594
Bipin Ravi7f565472021-03-31 10:10:27 -0500595 /* ---------------------------------------------------
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100596 * Enable CPU power down bit in power control register
597 * No need to do cache maintenance here.
Bipin Ravi7f565472021-03-31 10:10:27 -0500598 * ---------------------------------------------------
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100599 */
600 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
601 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
602 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
Bipin Ravicc744bf2022-12-07 17:01:26 -0600603#if ERRATA_N2_2743089
604 mov x15, x30
605 bl cpu_get_rev_var
606 bl errata_n2_2743089_wa
607 mov x30, x15
608#endif /* ERRATA_N2_2743089 */
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100609 isb
610 ret
611endfunc neoverse_n2_core_pwr_dwn
612
613#if REPORT_ERRATA
614/*
615 * Errata printing function for Neoverse N2 cores. Must follow AAPCS.
616 */
617func neoverse_n2_errata_report
nayanpatel-arm277581e2021-08-06 17:46:10 -0700618 stp x8, x30, [sp, #-16]!
619
620 bl cpu_get_rev_var
621 mov x8, x0
622
623 /*
624 * Report all errata. The revision-variant information is passed to
625 * checking functions of each errata.
626 */
627 report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
Bipin Ravieb35e852021-03-30 16:08:32 -0500628 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
Bipin Ravi7f565472021-03-31 10:10:27 -0500629 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -0700630 report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
Bipin Ravi0ba631c2021-09-01 01:36:43 -0500631 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -0700632 report_errata ERRATA_N2_2138953, neoverse_n2, 2138953
nayanpatel-arm2f153992021-10-06 15:31:24 -0700633 report_errata ERRATA_N2_2242415, neoverse_n2, 2242415
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700634 report_errata ERRATA_N2_2138958, neoverse_n2, 2138958
nayanpatel-armfed98132021-10-07 17:59:33 -0700635 report_errata ERRATA_N2_2242400, neoverse_n2, 2242400
nayanpatel-arm45b9f6f2021-10-20 17:30:46 -0700636 report_errata ERRATA_N2_2280757, neoverse_n2, 2280757
Boyan Karatotevd3f8b4d2022-10-03 14:07:08 +0100637 report_errata ERRATA_N2_2326639, neoverse_n2, 2326639
Akram Ahmadb621bda2022-07-18 12:27:29 +0100638 report_errata ERRATA_N2_2376738, neoverse_n2, 2376738
Daniel Boulby1af2b112022-07-06 14:33:13 +0100639 report_errata ERRATA_N2_2388450, neoverse_n2, 2388450
Bipin Ravicc744bf2022-12-07 17:01:26 -0600640 report_errata ERRATA_N2_2743089, neoverse_n2, 2743089
Bipin Ravi86499742022-01-18 01:59:06 -0600641 report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960
Bipin Raviaf40d692021-12-22 14:35:21 -0600642 report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941
nayanpatel-arm277581e2021-08-06 17:46:10 -0700643
644 ldp x8, x30, [sp], #16
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100645 ret
646endfunc neoverse_n2_errata_report
647#endif
648
649 /* ---------------------------------------------
650 * This function provides Neoverse N2 specific
651 * register information for crash reporting.
652 * It needs to return with x6 pointing to
653 * a list of register names in ASCII and
654 * x8 - x15 having values of registers to be
655 * reported.
656 * ---------------------------------------------
657 */
658.section .rodata.neoverse_n2_regs, "aS"
659neoverse_n2_regs: /* The ASCII list of register names to be reported */
660 .asciz "cpupwrctlr_el1", ""
661
662func neoverse_n2_cpu_reg_dump
663 adr x6, neoverse_n2_regs
664 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1
665 ret
666endfunc neoverse_n2_cpu_reg_dump
667
668declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \
669 neoverse_n2_reset_func, \
670 neoverse_n2_core_pwr_dwn