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Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01001/*
Masahiro Yamada0b67e562020-03-09 17:39:48 +09002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01005 */
6
7#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Masahiro Yamada0b67e562020-03-09 17:39:48 +09009#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/xlat_tables/xlat_tables_defs.h>
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010011
12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
13OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
14ENTRY(bl2u_entrypoint)
15
16MEMORY {
17 RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
18}
19
Chris Kay4b7660a2022-09-29 14:36:53 +010020SECTIONS {
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010021 . = BL2U_BASE;
Chris Kay4b7660a2022-09-29 14:36:53 +010022
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000023 ASSERT(. == ALIGN(PAGE_SIZE),
Chris Kay4b7660a2022-09-29 14:36:53 +010024 "BL2U_BASE address is not aligned on a page boundary.")
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010025
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010026#if SEPARATE_CODE_AND_RODATA
27 .text . : {
28 __TEXT_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010029
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010030 *bl2u_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050031 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010032 *(.vectors)
Chris Kay4b7660a2022-09-29 14:36:53 +010033
Roberto Vargasd93fde32018-04-11 11:53:31 +010034 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +010035
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010036 __TEXT_END__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010037 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010038
Chris Kay4b7660a2022-09-29 14:36:53 +010039 /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
40 .ARM.extab . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010041 *(.ARM.extab* .gnu.linkonce.armextab.*)
Chris Kay4b7660a2022-09-29 14:36:53 +010042 } >RAM
Roberto Vargas1d04c632018-05-10 11:01:16 +010043
Chris Kay4b7660a2022-09-29 14:36:53 +010044 .ARM.exidx . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010045 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
Chris Kay4b7660a2022-09-29 14:36:53 +010046 } >RAM
Roberto Vargas1d04c632018-05-10 11:01:16 +010047
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010048 .rodata . : {
49 __RODATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050050 *(SORT_BY_ALIGNMENT(.rodata*))
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090051
Chris Kay4b7660a2022-09-29 14:36:53 +010052 RODATA_COMMON
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090053
Roberto Vargasd93fde32018-04-11 11:53:31 +010054 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010055 __RODATA_END__ = .;
56 } >RAM
Chris Kay4b7660a2022-09-29 14:36:53 +010057#else /* SEPARATE_CODE_AND_RODATA */
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010058 ro . : {
59 __RO_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010060
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010061 *bl2u_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050062 *(SORT_BY_ALIGNMENT(.text*))
63 *(SORT_BY_ALIGNMENT(.rodata*))
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010064
Chris Kay4b7660a2022-09-29 14:36:53 +010065 RODATA_COMMON
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090066
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010067 *(.vectors)
Chris Kay4b7660a2022-09-29 14:36:53 +010068
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010069 __RO_END_UNALIGNED__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010070
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010071 /*
Chris Kay4b7660a2022-09-29 14:36:53 +010072 * Memory page(s) mapped to this section will be marked as read-only,
73 * executable. No RW data from the next section must creep in. Ensure
74 * that the rest of the current memory page is unused.
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010075 */
Roberto Vargasd93fde32018-04-11 11:53:31 +010076 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +010077
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010078 __RO_END__ = .;
79 } >RAM
Chris Kay4b7660a2022-09-29 14:36:53 +010080#endif /* SEPARATE_CODE_AND_RODATA */
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010081
Chris Kay4b7660a2022-09-29 14:36:53 +010082 __RW_START__ = .;
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010083
Masahiro Yamadac5864d82020-04-22 10:50:12 +090084 DATA_SECTION >RAM
Masahiro Yamada403990e2020-04-07 13:04:24 +090085 STACK_SECTION >RAM
Masahiro Yamadadd053b62020-03-26 13:16:33 +090086 BSS_SECTION >RAM
Masahiro Yamada0b67e562020-03-09 17:39:48 +090087 XLAT_TABLE_SECTION >RAM
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010088
89#if USE_COHERENT_MEM
90 /*
Chris Kay4b7660a2022-09-29 14:36:53 +010091 * The base address of the coherent memory section must be page-aligned to
92 * guarantee that the coherent data are stored on their own pages and are
93 * not mixed with normal data. This is required to set up the correct
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010094 * memory attributes for the coherent data page tables.
95 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000096 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010097 __COHERENT_RAM_START__ = .;
98 *(tzfw_coherent_mem)
99 __COHERENT_RAM_END_UNALIGNED__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +0100100
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100101 /*
Chris Kay4b7660a2022-09-29 14:36:53 +0100102 * Memory page(s) mapped to this section will be marked as device
103 * memory. No other unexpected data must creep in. Ensure the rest of
104 * the current memory page is unused.
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100105 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100106 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +0100107
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100108 __COHERENT_RAM_END__ = .;
109 } >RAM
Chris Kay4b7660a2022-09-29 14:36:53 +0100110#endif /* USE_COHERENT_MEM */
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100111
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100112 __RW_END__ = .;
113 __BL2U_END__ = .;
114
115 __BSS_SIZE__ = SIZEOF(.bss);
116
117 ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
118}