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Dan Handley9df48042015-03-19 18:58:55 +00001/*
David Cunado2e36de82017-01-19 10:26:16 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#ifndef __ARM_DEF_H__
7#define __ARM_DEF_H__
8
Soby Mathewfec4eb72015-07-01 16:16:20 +01009#include <arch.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <common_def.h>
11#include <platform_def.h>
Juan Castillo9b265a82015-05-07 14:52:44 +010012#include <tbbr_img_def.h>
Scott Brandenbf404c02017-04-10 11:45:52 -070013#include <utils_def.h>
Antonio Nino Diaz719bf852017-02-23 17:22:58 +000014#include <xlat_tables_defs.h>
Dan Handley9df48042015-03-19 18:58:55 +000015
16
17/******************************************************************************
18 * Definitions common to all ARM standard platforms
19 *****************************************************************************/
20
Juan Castillo7d199412015-12-14 09:35:25 +000021/* Special value used to verify platform parameters from BL2 to BL31 */
Dan Handley9df48042015-03-19 18:58:55 +000022#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
23
Soby Mathewa869de12015-05-08 10:18:59 +010024#define ARM_SYSTEM_COUNT 1
Dan Handley9df48042015-03-19 18:58:55 +000025
26#define ARM_CACHE_WRITEBACK_SHIFT 6
27
Soby Mathewfec4eb72015-07-01 16:16:20 +010028/*
29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
30 * power levels have a 1:1 mapping with the MPIDR affinity levels.
31 */
32#define ARM_PWR_LVL0 MPIDR_AFFLVL0
33#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010034#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Soby Mathewfec4eb72015-07-01 16:16:20 +010035
36/*
37 * Macros for local power states in ARM platforms encoded by State-ID field
38 * within the power-state parameter.
39 */
40/* Local power state for power domains in Run state. */
41#define ARM_LOCAL_STATE_RUN 0
42/* Local power state for retention. Valid only for CPU power domains */
43#define ARM_LOCAL_STATE_RET 1
44/* Local power state for OFF/power-down. Valid for CPU and cluster power
45 domains */
46#define ARM_LOCAL_STATE_OFF 2
47
Dan Handley9df48042015-03-19 18:58:55 +000048/* Memory location options for TSP */
49#define ARM_TRUSTED_SRAM_ID 0
50#define ARM_TRUSTED_DRAM_ID 1
51#define ARM_DRAM_ID 2
52
53/* The first 4KB of Trusted SRAM are used as shared memory */
54#define ARM_TRUSTED_SRAM_BASE 0x04000000
55#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
56#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
57
58/* The remaining Trusted SRAM is used to load the BL images */
59#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
60 ARM_SHARED_RAM_SIZE)
61#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
62 ARM_SHARED_RAM_SIZE)
63
64/*
65 * The top 16MB of DRAM1 is configured as secure access only using the TZC
66 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
67 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
68 */
David Cunado2e36de82017-01-19 10:26:16 +000069#define ARM_TZC_DRAM1_SIZE ULL(0x01000000)
Dan Handley9df48042015-03-19 18:58:55 +000070
71#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
72 ARM_DRAM1_SIZE - \
73 ARM_SCP_TZC_DRAM1_SIZE)
74#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
75#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
76 ARM_SCP_TZC_DRAM1_SIZE - 1)
77
78#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
79 ARM_DRAM1_SIZE - \
80 ARM_TZC_DRAM1_SIZE)
81#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
82 ARM_SCP_TZC_DRAM1_SIZE)
83#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
84 ARM_AP_TZC_DRAM1_SIZE - 1)
85
86
87#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
88#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
89 ARM_TZC_DRAM1_SIZE)
90#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
91 ARM_NS_DRAM1_SIZE - 1)
92
David Cunado2e36de82017-01-19 10:26:16 +000093#define ARM_DRAM1_BASE ULL(0x80000000)
94#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +000095#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
96 ARM_DRAM1_SIZE - 1)
97
David Cunado2e36de82017-01-19 10:26:16 +000098#define ARM_DRAM2_BASE ULL(0x880000000)
Dan Handley9df48042015-03-19 18:58:55 +000099#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
100#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
101 ARM_DRAM2_SIZE - 1)
102
103#define ARM_IRQ_SEC_PHY_TIMER 29
104
105#define ARM_IRQ_SEC_SGI_0 8
106#define ARM_IRQ_SEC_SGI_1 9
107#define ARM_IRQ_SEC_SGI_2 10
108#define ARM_IRQ_SEC_SGI_3 11
109#define ARM_IRQ_SEC_SGI_4 12
110#define ARM_IRQ_SEC_SGI_5 13
111#define ARM_IRQ_SEC_SGI_6 14
112#define ARM_IRQ_SEC_SGI_7 15
113
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000114/*
115 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
116 * terminology. On a GICv2 system or mode, the lists will be merged and treated
117 * as Group 0 interrupts.
118 */
119#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
120 ARM_IRQ_SEC_SGI_1, \
121 ARM_IRQ_SEC_SGI_2, \
122 ARM_IRQ_SEC_SGI_3, \
123 ARM_IRQ_SEC_SGI_4, \
124 ARM_IRQ_SEC_SGI_5, \
125 ARM_IRQ_SEC_SGI_7
126
127#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
128 ARM_IRQ_SEC_SGI_6
129
Dan Handley9df48042015-03-19 18:58:55 +0000130#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
131 ARM_SHARED_RAM_BASE, \
132 ARM_SHARED_RAM_SIZE, \
Juan Castillo2e86cb12016-01-13 15:01:09 +0000133 MT_DEVICE | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000134
135#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
136 ARM_NS_DRAM1_BASE, \
137 ARM_NS_DRAM1_SIZE, \
138 MT_MEMORY | MT_RW | MT_NS)
139
140#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
141 TSP_SEC_MEM_BASE, \
142 TSP_SEC_MEM_SIZE, \
143 MT_MEMORY | MT_RW | MT_SECURE)
144
David Wang0ba499f2016-03-07 11:02:57 +0800145#if ARM_BL31_IN_DRAM
146#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
147 BL31_BASE, \
148 PLAT_ARM_MAX_BL31_SIZE, \
149 MT_MEMORY | MT_RW | MT_SECURE)
150#endif
Dan Handley9df48042015-03-19 18:58:55 +0000151
152/*
153 * The number of regions like RO(code), coherent and data required by
154 * different BL stages which need to be mapped in the MMU.
155 */
156#if USE_COHERENT_MEM
157#define ARM_BL_REGIONS 3
158#else
159#define ARM_BL_REGIONS 2
160#endif
161
162#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
163 ARM_BL_REGIONS)
164
165/* Memory mapped Generic timer interfaces */
166#define ARM_SYS_CNTCTL_BASE 0x2a430000
167#define ARM_SYS_CNTREAD_BASE 0x2a800000
168#define ARM_SYS_TIMCTL_BASE 0x2a810000
169
170#define ARM_CONSOLE_BAUDRATE 115200
171
Juan Castillob6132f12015-10-06 14:01:35 +0100172/* Trusted Watchdog constants */
173#define ARM_SP805_TWDG_BASE 0x2a490000
174#define ARM_SP805_TWDG_CLK_HZ 32768
175/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
176 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
177#define ARM_TWDG_TIMEOUT_SEC 128
178#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
179 ARM_TWDG_TIMEOUT_SEC)
180
Dan Handley9df48042015-03-19 18:58:55 +0000181/******************************************************************************
182 * Required platform porting definitions common to all ARM standard platforms
183 *****************************************************************************/
184
Antonio Nino Diazf6601042016-12-13 13:48:31 +0000185#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
186#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
Dan Handley9df48042015-03-19 18:58:55 +0000187
Soby Mathewfec4eb72015-07-01 16:16:20 +0100188/*
189 * This macro defines the deepest retention state possible. A higher state
190 * id will represent an invalid or a power down state.
191 */
192#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
193
194/*
195 * This macro defines the deepest power down states possible. Any state ID
196 * higher than this is invalid.
197 */
198#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
199
Dan Handley9df48042015-03-19 18:58:55 +0000200/*
201 * Some data must be aligned on the biggest cache line size in the platform.
202 * This is known only to the platform as it might have a combination of
203 * integrated and external caches.
204 */
205#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
206
Dan Handley9df48042015-03-19 18:58:55 +0000207
208/*******************************************************************************
209 * BL1 specific defines.
210 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
211 * addresses.
212 ******************************************************************************/
213#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
214#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
215 + PLAT_ARM_TRUSTED_ROM_SIZE)
216/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000217 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000218 */
Dan Handley9df48042015-03-19 18:58:55 +0000219#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
220 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000221 PLAT_ARM_MAX_BL1_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000222#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
223
224/*******************************************************************************
225 * BL2 specific defines.
226 ******************************************************************************/
David Wang0ba499f2016-03-07 11:02:57 +0800227#if ARM_BL31_IN_DRAM
228/*
229 * BL31 is loaded in the DRAM.
230 * Put BL2 just below BL1.
231 */
232#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
233#define BL2_LIMIT BL1_RW_BASE
234#else
Dan Handley9df48042015-03-19 18:58:55 +0000235/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000236 * Put BL2 just below BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000237 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000238#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000239#define BL2_LIMIT BL31_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800240#endif
Dan Handley9df48042015-03-19 18:58:55 +0000241
242/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000243 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000244 ******************************************************************************/
David Wang0ba499f2016-03-07 11:02:57 +0800245#if ARM_BL31_IN_DRAM
246/*
247 * Put BL31 at the bottom of TZC secured DRAM
248 */
249#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
250#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
251 PLAT_ARM_MAX_BL31_SIZE)
252#else
Dan Handley9df48042015-03-19 18:58:55 +0000253/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000254 * Put BL31 at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000255 */
256#define BL31_BASE (ARM_BL_RAM_BASE + \
257 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000258 PLAT_ARM_MAX_BL31_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000259#define BL31_PROGBITS_LIMIT BL1_RW_BASE
260#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800261#endif
Dan Handley9df48042015-03-19 18:58:55 +0000262
263/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000264 * BL32 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000265 ******************************************************************************/
266/*
267 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
268 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
269 * controller.
270 */
David Wang0ba499f2016-03-07 11:02:57 +0800271#if ARM_BL31_IN_DRAM
272# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
273 PLAT_ARM_MAX_BL31_SIZE)
274# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
275 PLAT_ARM_MAX_BL31_SIZE)
276# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
277 PLAT_ARM_MAX_BL31_SIZE)
278# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
279 ARM_AP_TZC_DRAM1_SIZE)
280#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
Dan Handley9df48042015-03-19 18:58:55 +0000281# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
282# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
283# define TSP_PROGBITS_LIMIT BL2_BASE
284# define BL32_BASE ARM_BL_RAM_BASE
285# define BL32_LIMIT BL31_BASE
286#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
287# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
288# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
289# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
290# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
291 + (1 << 21))
292#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
293# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
294# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
295# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
296# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
297 ARM_AP_TZC_DRAM1_SIZE)
298#else
299# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
300#endif
301
Soby Mathew0d268dc2016-07-11 14:13:56 +0100302/* BL32 is mandatory in AArch32 */
303#ifndef AARCH32
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100304#ifdef SPD_none
305#undef BL32_BASE
306#endif /* SPD_none */
Soby Mathew0d268dc2016-07-11 14:13:56 +0100307#endif
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100308
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100309/*******************************************************************************
310 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
311 ******************************************************************************/
312#define BL2U_BASE BL2_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800313#if ARM_BL31_IN_DRAM
314#define BL2U_LIMIT BL1_RW_BASE
315#else
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100316#define BL2U_LIMIT BL31_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800317#endif
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100318#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Yatharth Kocharf11b29a2016-02-01 11:04:46 +0000319#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100320
Dan Handley9df48042015-03-19 18:58:55 +0000321/*
322 * ID of the secure physical generic timer interrupt used by the TSP.
323 */
324#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
325
326
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100327/*
328 * One cache line needed for bakery locks on ARM platforms
329 */
330#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
331
332
Dan Handley9df48042015-03-19 18:58:55 +0000333#endif /* __ARM_DEF_H__ */