blob: 5fa7218421e97f91c7b0e0e3c9ae303cc92a3ff0 [file] [log] [blame]
Haojian Zhuang602362d2017-06-01 12:15:14 +08001#
Masahiro Yamada4d156802018-01-26 11:42:01 +09002# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang602362d2017-06-01 12:15:14 +08003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Victor Chong2d9a42d2017-08-17 15:21:10 +09007# Enable version2 of image loading
8LOAD_IMAGE_V2 := 1
9
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080010# Non-TF Boot ROM
11BL2_AT_EL3 := 1
12
Victor Chong91287682017-05-28 00:14:37 +090013# On Hikey960, the TSP can execute from TZC secure area in DRAM.
Victor Chong4d64c2b2018-02-01 00:37:49 +090014HIKEY960_TSP_RAM_LOCATION ?= dram
Victor Chong91287682017-05-28 00:14:37 +090015ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram)
16 HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_DRAM_ID
17else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram)
Victor Chong4d64c2b2018-02-01 00:37:49 +090018 HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_SRAM_ID
Victor Chong91287682017-05-28 00:14:37 +090019else
20 $(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value")
21endif
22
Haojian Zhuang602362d2017-06-01 12:15:14 +080023CRASH_CONSOLE_BASE := PL011_UART6_BASE
24COLD_BOOT_SINGLE_CPU := 1
Kaihua Zhong39ff2ee2018-07-16 17:33:48 +080025PLAT_PL061_MAX_GPIOS := 176
Haojian Zhuang602362d2017-06-01 12:15:14 +080026PROGRAMMABLE_RESET_ADDRESS := 1
David Cunadoc5b0c0f2017-10-31 23:19:21 +000027ENABLE_SVE_FOR_NS := 0
Haojian Zhuang602362d2017-06-01 12:15:14 +080028
29# Process flags
Victor Chong91287682017-05-28 00:14:37 +090030$(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))
Haojian Zhuang602362d2017-06-01 12:15:14 +080031$(eval $(call add_define,CRASH_CONSOLE_BASE))
Kaihua Zhong39ff2ee2018-07-16 17:33:48 +080032$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Haojian Zhuang602362d2017-06-01 12:15:14 +080033
Victor Chong7d787f52017-08-16 13:53:56 +090034# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
35# in the FIP if the platform requires.
36ifneq ($(BL32_EXTRA1),)
Masahiro Yamada9c5ca522018-01-26 11:42:01 +090037$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1))
Victor Chong7d787f52017-08-16 13:53:56 +090038endif
39ifneq ($(BL32_EXTRA2),)
Masahiro Yamada9c5ca522018-01-26 11:42:01 +090040$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
Victor Chong7d787f52017-08-16 13:53:56 +090041endif
42
Haojian Zhuang602362d2017-06-01 12:15:14 +080043ENABLE_PLAT_COMPAT := 0
44
45USE_COHERENT_MEM := 1
46
47PLAT_INCLUDES := -Iinclude/common/tbbr \
48 -Iplat/hisilicon/hikey960/include
49
50PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
51 drivers/delay_timer/delay_timer.c \
52 drivers/delay_timer/generic_delay_timer.c \
53 lib/aarch64/xlat_tables.c \
54 plat/hisilicon/hikey960/aarch64/hikey960_common.c \
55 plat/hisilicon/hikey960/hikey960_boardid.c
56
57HIKEY960_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
58 drivers/arm/gic/v2/gicv2_main.c \
59 drivers/arm/gic/v2/gicv2_helpers.c \
60 plat/common/plat_gicv2.c
61
62BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
Kaihua Zhong39ff2ee2018-07-16 17:33:48 +080063 drivers/arm/pl061/pl061_gpio.c \
64 drivers/gpio/gpio.c \
Haojian Zhuang602362d2017-06-01 12:15:14 +080065 drivers/io/io_block.c \
66 drivers/io/io_fip.c \
67 drivers/io/io_storage.c \
68 drivers/synopsys/ufs/dw_ufs.c \
69 drivers/ufs/ufs.c \
70 lib/cpus/aarch64/cortex_a53.S \
71 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
Haojian Zhuangd82e29d2018-03-05 13:20:33 +080072 plat/hisilicon/hikey960/hikey960_bl1_setup.c \
73 plat/hisilicon/hikey960/hikey960_bl_common.c \
Haojian Zhuang602362d2017-06-01 12:15:14 +080074 plat/hisilicon/hikey960/hikey960_io_storage.c \
75 ${HIKEY960_GIC_SOURCES}
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080076
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080077BL2_SOURCES += common/desc_image_load.c \
Kaihua Zhong39ff2ee2018-07-16 17:33:48 +080078 drivers/arm/pl061/pl061_gpio.c \
79 drivers/gpio/gpio.c \
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080080 drivers/io/io_block.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080081 drivers/io/io_fip.c \
82 drivers/io/io_storage.c \
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080083 drivers/synopsys/ufs/dw_ufs.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080084 drivers/ufs/ufs.c \
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080085 lib/cpus/aarch64/cortex_a53.S \
86 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080087 plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080088 plat/hisilicon/hikey960/hikey960_bl2_setup.c \
Haojian Zhuangd82e29d2018-03-05 13:20:33 +080089 plat/hisilicon/hikey960/hikey960_bl_common.c \
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080090 plat/hisilicon/hikey960/hikey960_image_load.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080091 plat/hisilicon/hikey960/hikey960_io_storage.c \
92 plat/hisilicon/hikey960/hikey960_mcu_load.c
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080093
Victor Chong7d787f52017-08-16 13:53:56 +090094ifeq (${SPD},opteed)
95BL2_SOURCES += lib/optee/optee_utils.c
96endif
Victor Chong2d9a42d2017-08-17 15:21:10 +090097
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080098BL31_SOURCES += drivers/arm/cci/cci.c \
99 lib/cpus/aarch64/cortex_a53.S \
100 lib/cpus/aarch64/cortex_a72.S \
101 lib/cpus/aarch64/cortex_a73.S \
102 plat/common/aarch64/plat_psci_common.c \
103 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
104 plat/hisilicon/hikey960/hikey960_bl31_setup.c \
105 plat/hisilicon/hikey960/hikey960_pm.c \
106 plat/hisilicon/hikey960/hikey960_topology.c \
107 plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c \
108 plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c \
109 ${HIKEY960_GIC_SOURCES}
Victor Chongcb27a352017-07-12 01:07:29 +0900110
111# Enable workarounds for selected Cortex-A53 errata.
112ERRATA_A53_836870 := 1
113ERRATA_A53_843419 := 1
114ERRATA_A53_855873 := 1
Leo Yan453940d2017-11-22 17:10:39 +0800115
116FIP_ALIGN := 512