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Vikram Kanigiri510d87b2016-01-29 12:32:58 +00001/*
Summer Qin5ce394c2018-03-12 11:28:26 +08002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00005 */
6
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <common/debug.h>
12#include <drivers/arm/tzc_dmc500.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000013#include <plat/arm/common/plat_arm.h>
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000014
15/*******************************************************************************
16 * Initialize the DMC500-TrustZone Controller for ARM standard platforms.
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000017 * When booting an EL3 payload, this is simplified: we configure region 0 with
18 * secure access only and do not enable any other region.
19 ******************************************************************************/
Summer Qin5ce394c2018-03-12 11:28:26 +080020void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data,
21 const arm_tzc_regions_info_t *tzc_regions)
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000022{
Summer Qin5ce394c2018-03-12 11:28:26 +080023#ifndef EL3_PAYLOAD_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010024 unsigned int region_index = 1U;
Summer Qin5ce394c2018-03-12 11:28:26 +080025 const arm_tzc_regions_info_t *p;
26 const arm_tzc_regions_info_t init_tzc_regions[] = {
27 ARM_TZC_REGIONS_DEF,
28 {0}
29 };
30#endif
31
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000032 assert(plat_driver_data);
33
34 INFO("Configuring DMC-500 TZ Settings\n");
35
36 tzc_dmc500_driver_init(plat_driver_data);
37
38#ifndef EL3_PAYLOAD_BASE
Summer Qin5ce394c2018-03-12 11:28:26 +080039 if (tzc_regions == NULL)
40 p = init_tzc_regions;
41 else
42 p = tzc_regions;
43
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000044 /* Region 0 set to no access by default */
45 tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0);
46
Summer Qin5ce394c2018-03-12 11:28:26 +080047 /* Rest Regions set according to tzc_regions array */
48 for (; p->base != 0ULL; p++) {
49 tzc_dmc500_configure_region(region_index, p->base, p->end,
50 p->sec_attr, p->nsaid_permissions);
51 region_index++;
52 }
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000053
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010054 INFO("Total %u regions set.\n", region_index);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000055
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000056#else
57 /* Allow secure access only to DRAM for EL3 payloads */
58 tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0);
59#endif
60 /*
61 * Raise an exception if a NS device tries to access secure memory
62 * TODO: Add interrupt handling support.
63 */
64 tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR);
65
66 /*
67 * Flush the configuration settings to have an affect. Validate
68 * flush by checking FILTER_EN is set on region 1 attributes
69 * register.
70 */
71 tzc_dmc500_config_complete();
72
73 /*
74 * Wait for the flush to complete.
75 * TODO: Have a timeout for this loop
76 */
77 while (tzc_dmc500_verify_complete())
78 ;
79}