| Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | RESET_TO_BL31 := 1 |
| 8 | ifeq (${RESET_TO_BL31}, 0) |
| 9 | $(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") |
| 10 | endif |
| 11 | |
| Oliver Swede | 3769b3f | 2019-12-16 14:08:27 +0000 | [diff] [blame] | 12 | ifeq (${ENABLE_PIE}, 1) |
| 13 | override SEPARATE_CODE_AND_RODATA := 1 |
| 14 | endif |
| 15 | |
| Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 16 | CTX_INCLUDE_AARCH32_REGS := 0 |
| 17 | ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) |
| 18 | $(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") |
| 19 | endif |
| 20 | |
| 21 | ifeq (${TRUSTED_BOARD_BOOT}, 1) |
| 22 | $(error "TRUSTED_BOARD_BOOT must be disabled") |
| 23 | endif |
| 24 | |
| 25 | ifndef PRELOADED_BL33_BASE |
| 26 | $(error "PRELOADED_BL33_BASE is not set") |
| 27 | endif |
| 28 | |
| 29 | ifndef FPGA_PRELOADED_DTB_BASE |
| 30 | $(error "FPGA_PRELOADED_DTB_BASE is not set") |
| 31 | else |
| 32 | $(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) |
| 33 | endif |
| 34 | |
| 35 | # Treating this as a memory-constrained port for now |
| 36 | USE_COHERENT_MEM := 0 |
| 37 | |
| Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 38 | # This can be overridden depending on CPU(s) used in the FPGA image |
| Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 39 | HW_ASSISTED_COHERENCY := 1 |
| 40 | |
| Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 41 | FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S |
| 42 | |
| 43 | # select a different set of CPU files, depending on whether we compile for |
| 44 | # hardware assisted coherency cores or not |
| 45 | ifeq (${HW_ASSISTED_COHERENCY}, 0) |
| 46 | # Cores used without DSU |
| 47 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ |
| 48 | lib/cpus/aarch64/cortex_a53.S \ |
| 49 | lib/cpus/aarch64/cortex_a57.S \ |
| 50 | lib/cpus/aarch64/cortex_a72.S \ |
| 51 | lib/cpus/aarch64/cortex_a73.S |
| 52 | else |
| 53 | # AArch64-only cores |
| 54 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ |
| 55 | lib/cpus/aarch64/cortex_a76ae.S \ |
| 56 | lib/cpus/aarch64/cortex_a77.S \ |
| 57 | lib/cpus/aarch64/neoverse_n1.S \ |
| 58 | lib/cpus/aarch64/neoverse_e1.S \ |
| 59 | lib/cpus/aarch64/neoverse_zeus.S \ |
| 60 | lib/cpus/aarch64/cortex_hercules.S \ |
| 61 | lib/cpus/aarch64/cortex_hercules_ae.S \ |
| 62 | lib/cpus/aarch64/cortex_a65.S \ |
| 63 | lib/cpus/aarch64/cortex_a65ae.S |
| 64 | # AArch64/AArch32 cores |
| 65 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ |
| 66 | lib/cpus/aarch64/cortex_a75.S |
| 67 | endif |
| Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 68 | |
| Manish Pandey | b21cad7 | 2020-04-03 18:59:20 +0100 | [diff] [blame] | 69 | # GIC-600 configuration |
| 70 | GICV3_IMPL := GIC600 |
| 71 | |
| 72 | # Include GICv3 driver files |
| 73 | include drivers/arm/gic/v3/gicv3.mk |
| 74 | |
| 75 | FPGA_GIC_SOURCES := ${GICV3_SOURCES} \ |
| Oliver Swede | b51da81 | 2019-12-03 14:08:21 +0000 | [diff] [blame] | 76 | plat/common/plat_gicv3.c \ |
| 77 | plat/arm/board/arm_fpga/fpga_gicv3.c |
| Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 78 | |
| 79 | PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include |
| 80 | |
| 81 | PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S |
| 82 | |
| 83 | BL31_SOURCES += drivers/delay_timer/delay_timer.c \ |
| 84 | drivers/delay_timer/generic_delay_timer.c \ |
| 85 | drivers/arm/pl011/${ARCH}/pl011_console.S \ |
| 86 | plat/common/plat_psci_common.c \ |
| 87 | plat/arm/board/arm_fpga/fpga_pm.c \ |
| 88 | plat/arm/board/arm_fpga/fpga_topology.c \ |
| 89 | plat/arm/board/arm_fpga/fpga_console.c \ |
| 90 | plat/arm/board/arm_fpga/fpga_bl31_setup.c \ |
| 91 | ${FPGA_CPU_LIBS} \ |
| 92 | ${FPGA_GIC_SOURCES} |
| 93 | |
| 94 | all: bl31 |