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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#include <assert.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -08008#include <bl31.h>
Isla Mitchelle3631462017-07-14 10:46:32 +01009#include <bl_common.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -080010#include <console.h>
11#include <debug.h>
12#include <errno.h>
13#include <plat_arm.h>
14#include <platform.h>
15#include "zynqmp_private.h"
16
Soren Brinkmann6d1ba582016-07-08 14:45:14 -070017#define BL31_END (unsigned long)(&__BL31_END__)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080018
Soren Brinkmann76fcae32016-03-06 20:16:27 -080019static entry_point_info_t bl32_image_ep_info;
20static entry_point_info_t bl33_image_ep_info;
21
22/*
23 * Return a pointer to the 'entry_point_info' structure of the next image for
24 * the security state specified. BL33 corresponds to the non-secure image type
25 * while BL32 corresponds to the secure image type. A NULL pointer is returned
26 * if the image does not exist.
27 */
28entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
29{
30 assert(sec_state_is_valid(type));
31
32 if (type == NON_SECURE)
33 return &bl33_image_ep_info;
34
35 return &bl32_image_ep_info;
36}
37
38/*
39 * Perform any BL31 specific platform actions. Here is an opportunity to copy
40 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
41 * are lost (potentially). This needs to be done before the MMU is initialized
42 * so that the memory layout can be used while creating page tables.
43 */
44void bl31_early_platform_setup(bl31_params_t *from_bl2,
45 void *plat_params_from_bl2)
46{
47 /* Initialize the console to provide early debug support */
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -070048 console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(),
Soren Brinkmann76fcae32016-03-06 20:16:27 -080049 ZYNQMP_UART_BAUDRATE);
50
51 /* Initialize the platform config for future decision making */
52 zynqmp_config_setup();
53
54 /* There are no parameters from BL2 if BL31 is a reset vector */
55 assert(from_bl2 == NULL);
56 assert(plat_params_from_bl2 == NULL);
57
58 /*
59 * Do initial security configuration to allow DRAM/device access. On
60 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but
61 * other platforms might have more programmable security devices
62 * present.
63 */
64
Michal Simekef8f5592015-06-15 14:22:50 +020065 /* Populate common information for BL32 and BL33 */
Soren Brinkmann76fcae32016-03-06 20:16:27 -080066 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
67 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080068 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080069 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
70
Michal Simekef8f5592015-06-15 14:22:50 +020071 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
72 /* use build time defaults in JTAG boot mode */
73 bl32_image_ep_info.pc = BL32_BASE;
74 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
75 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
76 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
77 DISABLE_ALL_EXCEPTIONS);
78 } else {
79 /* use parameters from FSBL */
80 fsbl_atf_handover(&bl32_image_ep_info, &bl33_image_ep_info);
81 }
82
83 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080084 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
85}
86
Naga Sureshkumar Rellicf4e7142016-07-01 12:46:43 +053087/* Enable the test setup */
88#ifndef ZYNQMP_TESTING
89static void zynqmp_testing_setup(void) { }
90#else
91static void zynqmp_testing_setup(void)
92{
93 uint32_t actlr_el3, actlr_el2;
94
95 /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */
96 actlr_el3 = read_actlr_el3();
97 actlr_el2 = read_actlr_el2();
98
99 actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
100 actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
101 write_actlr_el3(actlr_el3);
102 write_actlr_el2(actlr_el2);
103}
104#endif
105
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800106void bl31_platform_setup(void)
107{
108 /* Initialize the gic cpu and distributor interfaces */
109 plat_arm_gic_driver_init();
110 plat_arm_gic_init();
Naga Sureshkumar Rellicf4e7142016-07-01 12:46:43 +0530111 zynqmp_testing_setup();
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800112}
113
114void bl31_plat_runtime_setup(void)
115{
116}
117
118/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100119 * Perform the very early platform specific architectural setup here.
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800120 */
121void bl31_plat_arch_setup(void)
122{
123 plat_arm_interconnect_init();
124 plat_arm_interconnect_enter_coherency();
125
Soren Brinkmann6d1ba582016-07-08 14:45:14 -0700126 arm_setup_page_tables(BL31_BASE,
127 BL31_END - BL31_BASE,
128 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900129 BL_CODE_END,
Soren Brinkmann6d1ba582016-07-08 14:45:14 -0700130 BL_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900131 BL_RO_DATA_END,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900132 BL_COHERENT_RAM_BASE,
133 BL_COHERENT_RAM_END);
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100134 enable_mmu_el3(0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800135}