Samuel Holland | e62c5dd | 2019-10-20 22:23:33 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <drivers/allwinner/axp.h> |
| 8 | |
| 9 | const uint8_t axp_chip_id = AXP805_CHIP_ID; |
| 10 | const char *const axp_compatible = "x-powers,axp805"; |
| 11 | |
Andre Przywara | 71b5a1d | 2021-11-01 00:17:37 +0000 | [diff] [blame] | 12 | #if SUNXI_SETUP_REGULATORS == 1 |
Samuel Holland | e62c5dd | 2019-10-20 22:23:33 -0500 | [diff] [blame] | 13 | /* |
| 14 | * The "dcdcd" split changes the step size by a factor of 5, not 2; |
| 15 | * disallow values above the split to maintain accuracy. |
| 16 | */ |
| 17 | const struct axp_regulator axp_regulators[] = { |
| 18 | {"dcdca", 600, 1520, 10, 50, 0x12, 0x10, 0}, |
| 19 | {"dcdcb", 1000, 2550, 50, NA, 0x13, 0x10, 1}, |
| 20 | {"dcdcc", 600, 1520, 10, 50, 0x14, 0x10, 2}, |
| 21 | {"dcdcd", 600, 1500, 20, NA, 0x15, 0x10, 3}, |
| 22 | {"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4}, |
| 23 | {"aldo1", 700, 3300, 100, NA, 0x17, 0x10, 5}, |
| 24 | {"aldo2", 700, 3300, 100, NA, 0x18, 0x10, 6}, |
| 25 | {"aldo3", 700, 3300, 100, NA, 0x19, 0x10, 7}, |
| 26 | {"bldo1", 700, 1900, 100, NA, 0x20, 0x11, 0}, |
| 27 | {"bldo2", 700, 1900, 100, NA, 0x21, 0x11, 1}, |
| 28 | {"bldo3", 700, 1900, 100, NA, 0x22, 0x11, 2}, |
| 29 | {"bldo4", 700, 1900, 100, NA, 0x23, 0x11, 3}, |
| 30 | {"cldo1", 700, 3300, 100, NA, 0x24, 0x11, 4}, |
| 31 | {"cldo2", 700, 4200, 100, 27, 0x25, 0x11, 5}, |
| 32 | {"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6}, |
| 33 | {} |
| 34 | }; |
Andre Przywara | 71b5a1d | 2021-11-01 00:17:37 +0000 | [diff] [blame] | 35 | #endif |