| Karl Li | eb62949 | 2023-04-27 14:00:10 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef APUSYS_RV_MBOX_MPU_H |
| 8 | #define APUSYS_RV_MBOX_MPU_H |
| 9 | |
| 10 | #define MPU_EN (0) |
| 11 | #define MPU_DIS (1) |
| 12 | #define MBOX0_TX_DOMAIN (0) |
| 13 | #define MBOX0_TX_NS (1) |
| 14 | #define MBOX4_RX_DOMAIN (0) |
| 15 | #define MBOX4_RX_NS (0) |
| 16 | #define MBOX5_TX_DOMAIN (3) |
| 17 | #define MBOX5_TX_NS (0) |
| 18 | #define MBOXN_RX_DOMAIN (5) |
| 19 | #define MBOXN_RX_NS (1) |
| 20 | #define MBOXN_TX_DOMAIN (0) |
| 21 | #define MBOXN_TX_NS (0) |
| 22 | |
| 23 | struct mbox_mpu_setting { |
| 24 | uint32_t no_mpu; |
| 25 | uint32_t rx_ns; |
| 26 | uint32_t rx_domain; |
| 27 | uint32_t tx_ns; |
| 28 | uint32_t tx_domain; |
| 29 | }; |
| 30 | |
| 31 | static const struct mbox_mpu_setting mbox_mpu_setting_tab[] = { |
| 32 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX0_TX_NS, MBOX0_TX_DOMAIN }, |
| 33 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, |
| 34 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, |
| 35 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, |
| 36 | { MPU_DIS, MBOX4_RX_NS, MBOX4_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, |
| 37 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX5_TX_NS, MBOX5_TX_DOMAIN }, |
| 38 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, |
| 39 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, |
| 40 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, |
| 41 | { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, |
| 42 | }; |
| 43 | |
| 44 | #define APU_MBOX_NUM ARRAY_SIZE(mbox_mpu_setting_tab) |
| 45 | |
| 46 | #endif /* APUSYS_RV_MBOX_MPU_H */ |