| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2020, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef NEOVERSE_N_COMMON_H |
| 8 | #define NEOVERSE_N_COMMON_H |
| 9 | |
| 10 | /****************************************************************************** |
| 11 | * Neoverse Nx CPU Configuration register definitions |
| 12 | *****************************************************************************/ |
| 13 | #define CPUCFR_EL1 S3_0_C15_C0_0 |
| 14 | |
| 15 | /* SCU bit of CPU Configuration Register, EL1 */ |
| 16 | #define SCU_SHIFT U(2) |
| 17 | |
| 18 | #endif /* NEOVERSE_N_COMMON_H */ |