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Joel Hutton2691bc62017-12-12 15:47:55 +00001/*
Govindraj Rajaeee28e72023-08-01 15:52:40 -05002 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
Joel Hutton2691bc62017-12-12 15:47:55 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <assert_macros.S>
9#include <asm_macros.S>
10
11 .globl amu_group0_cnt_read_internal
12 .globl amu_group0_cnt_write_internal
13 .globl amu_group1_cnt_read_internal
14 .globl amu_group1_cnt_write_internal
15 .globl amu_group1_set_evtype_internal
16
17/*
18 * uint64_t amu_group0_cnt_read_internal(int idx);
19 *
20 * Given `idx`, read the corresponding AMU counter
Dimitris Papastamose0848e92018-02-20 12:25:36 +000021 * and return it in `r0` and `r1`.
Joel Hutton2691bc62017-12-12 15:47:55 +000022 */
23func amu_group0_cnt_read_internal
24#if ENABLE_ASSERTIONS
25 /* `idx` should be between [0, 3] */
26 mov r1, r0
27 lsr r1, r1, #2
28 cmp r1, #0
29 ASM_ASSERT(eq)
30#endif
31
32 /*
33 * Given `idx` calculate address of ldcopr16/bx lr instruction pair
34 * in the table below.
35 */
36 adr r1, 1f
37 lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */
38 add r1, r1, r0
39 bx r1
401:
41 ldcopr16 r0, r1, AMEVCNTR00 /* index 0 */
42 bx lr
43 ldcopr16 r0, r1, AMEVCNTR01 /* index 1 */
44 bx lr
45 ldcopr16 r0, r1, AMEVCNTR02 /* index 2 */
46 bx lr
47 ldcopr16 r0, r1, AMEVCNTR03 /* index 3 */
48 bx lr
49endfunc amu_group0_cnt_read_internal
50
51/*
52 * void amu_group0_cnt_write_internal(int idx, uint64_t val);
53 *
54 * Given `idx`, write `val` to the corresponding AMU counter.
Dimitris Papastamose0848e92018-02-20 12:25:36 +000055 * `idx` is passed in `r0` and `val` is passed in `r2` and `r3`.
56 * `r1` is used as a scratch register.
Joel Hutton2691bc62017-12-12 15:47:55 +000057 */
58func amu_group0_cnt_write_internal
59#if ENABLE_ASSERTIONS
60 /* `idx` should be between [0, 3] */
Dimitris Papastamose0848e92018-02-20 12:25:36 +000061 mov r1, r0
62 lsr r1, r1, #2
63 cmp r1, #0
Joel Hutton2691bc62017-12-12 15:47:55 +000064 ASM_ASSERT(eq)
65#endif
66
67 /*
68 * Given `idx` calculate address of stcopr16/bx lr instruction pair
69 * in the table below.
70 */
Dimitris Papastamose0848e92018-02-20 12:25:36 +000071 adr r1, 1f
Joel Hutton2691bc62017-12-12 15:47:55 +000072 lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
Dimitris Papastamose0848e92018-02-20 12:25:36 +000073 add r1, r1, r0
74 bx r1
Joel Hutton2691bc62017-12-12 15:47:55 +000075
761:
Dimitris Papastamose0848e92018-02-20 12:25:36 +000077 stcopr16 r2, r3, AMEVCNTR00 /* index 0 */
johpow01fa59c6f2020-10-02 13:41:11 -050078 bx lr
Dimitris Papastamose0848e92018-02-20 12:25:36 +000079 stcopr16 r2, r3, AMEVCNTR01 /* index 1 */
johpow01fa59c6f2020-10-02 13:41:11 -050080 bx lr
Dimitris Papastamose0848e92018-02-20 12:25:36 +000081 stcopr16 r2, r3, AMEVCNTR02 /* index 2 */
johpow01fa59c6f2020-10-02 13:41:11 -050082 bx lr
Dimitris Papastamose0848e92018-02-20 12:25:36 +000083 stcopr16 r2, r3, AMEVCNTR03 /* index 3 */
johpow01fa59c6f2020-10-02 13:41:11 -050084 bx lr
Joel Hutton2691bc62017-12-12 15:47:55 +000085endfunc amu_group0_cnt_write_internal
86
Chris Kay925fda42021-05-25 10:42:56 +010087#if ENABLE_AMU_AUXILIARY_COUNTERS
Joel Hutton2691bc62017-12-12 15:47:55 +000088/*
89 * uint64_t amu_group1_cnt_read_internal(int idx);
90 *
91 * Given `idx`, read the corresponding AMU counter
Dimitris Papastamose0848e92018-02-20 12:25:36 +000092 * and return it in `r0` and `r1`.
Joel Hutton2691bc62017-12-12 15:47:55 +000093 */
94func amu_group1_cnt_read_internal
95#if ENABLE_ASSERTIONS
96 /* `idx` should be between [0, 15] */
Dimitris Papastamose0848e92018-02-20 12:25:36 +000097 mov r1, r0
98 lsr r1, r1, #4
99 cmp r1, #0
Joel Hutton2691bc62017-12-12 15:47:55 +0000100 ASM_ASSERT(eq)
101#endif
102
103 /*
104 * Given `idx` calculate address of ldcopr16/bx lr instruction pair
105 * in the table below.
106 */
107 adr r1, 1f
108 lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */
109 add r1, r1, r0
110 bx r1
111
1121:
Dimitris Papastamose0848e92018-02-20 12:25:36 +0000113 ldcopr16 r0, r1, AMEVCNTR10 /* index 0 */
114 bx lr
115 ldcopr16 r0, r1, AMEVCNTR11 /* index 1 */
116 bx lr
117 ldcopr16 r0, r1, AMEVCNTR12 /* index 2 */
118 bx lr
119 ldcopr16 r0, r1, AMEVCNTR13 /* index 3 */
120 bx lr
121 ldcopr16 r0, r1, AMEVCNTR14 /* index 4 */
122 bx lr
123 ldcopr16 r0, r1, AMEVCNTR15 /* index 5 */
124 bx lr
125 ldcopr16 r0, r1, AMEVCNTR16 /* index 6 */
126 bx lr
127 ldcopr16 r0, r1, AMEVCNTR17 /* index 7 */
128 bx lr
129 ldcopr16 r0, r1, AMEVCNTR18 /* index 8 */
130 bx lr
131 ldcopr16 r0, r1, AMEVCNTR19 /* index 9 */
132 bx lr
133 ldcopr16 r0, r1, AMEVCNTR1A /* index 10 */
134 bx lr
135 ldcopr16 r0, r1, AMEVCNTR1B /* index 11 */
136 bx lr
137 ldcopr16 r0, r1, AMEVCNTR1C /* index 12 */
138 bx lr
139 ldcopr16 r0, r1, AMEVCNTR1D /* index 13 */
140 bx lr
141 ldcopr16 r0, r1, AMEVCNTR1E /* index 14 */
142 bx lr
143 ldcopr16 r0, r1, AMEVCNTR1F /* index 15 */
144 bx lr
Joel Hutton2691bc62017-12-12 15:47:55 +0000145endfunc amu_group1_cnt_read_internal
146
147/*
148 * void amu_group1_cnt_write_internal(int idx, uint64_t val);
149 *
150 * Given `idx`, write `val` to the corresponding AMU counter.
Dimitris Papastamose0848e92018-02-20 12:25:36 +0000151 * `idx` is passed in `r0` and `val` is passed in `r2` and `r3`.
152 * `r1` is used as a scratch register.
Joel Hutton2691bc62017-12-12 15:47:55 +0000153 */
154func amu_group1_cnt_write_internal
155#if ENABLE_ASSERTIONS
156 /* `idx` should be between [0, 15] */
Dimitris Papastamose0848e92018-02-20 12:25:36 +0000157 mov r1, r0
158 lsr r1, r1, #4
159 cmp r1, #0
Joel Hutton2691bc62017-12-12 15:47:55 +0000160 ASM_ASSERT(eq)
161#endif
162
163 /*
164 * Given `idx` calculate address of ldcopr16/bx lr instruction pair
165 * in the table below.
166 */
Dimitris Papastamose0848e92018-02-20 12:25:36 +0000167 adr r1, 1f
Joel Hutton2691bc62017-12-12 15:47:55 +0000168 lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
Dimitris Papastamose0848e92018-02-20 12:25:36 +0000169 add r1, r1, r0
170 bx r1
Joel Hutton2691bc62017-12-12 15:47:55 +0000171
1721:
johpow01fa59c6f2020-10-02 13:41:11 -0500173 stcopr16 r2, r3, AMEVCNTR10 /* index 0 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000174 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500175 stcopr16 r2, r3, AMEVCNTR11 /* index 1 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000176 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500177 stcopr16 r2, r3, AMEVCNTR12 /* index 2 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000178 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500179 stcopr16 r2, r3, AMEVCNTR13 /* index 3 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000180 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500181 stcopr16 r2, r3, AMEVCNTR14 /* index 4 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000182 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500183 stcopr16 r2, r3, AMEVCNTR15 /* index 5 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000184 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500185 stcopr16 r2, r3, AMEVCNTR16 /* index 6 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000186 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500187 stcopr16 r2, r3, AMEVCNTR17 /* index 7 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000188 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500189 stcopr16 r2, r3, AMEVCNTR18 /* index 8 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000190 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500191 stcopr16 r2, r3, AMEVCNTR19 /* index 9 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000192 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500193 stcopr16 r2, r3, AMEVCNTR1A /* index 10 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000194 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500195 stcopr16 r2, r3, AMEVCNTR1B /* index 11 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000196 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500197 stcopr16 r2, r3, AMEVCNTR1C /* index 12 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000198 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500199 stcopr16 r2, r3, AMEVCNTR1D /* index 13 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000200 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500201 stcopr16 r2, r3, AMEVCNTR1E /* index 14 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000202 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500203 stcopr16 r2, r3, AMEVCNTR1F /* index 15 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000204 bx lr
205endfunc amu_group1_cnt_write_internal
206
207/*
208 * void amu_group1_set_evtype_internal(int idx, unsigned int val);
209 *
210 * Program the AMU event type register indexed by `idx`
211 * with the value `val`.
212 */
213func amu_group1_set_evtype_internal
214#if ENABLE_ASSERTIONS
215 /* `idx` should be between [0, 15] */
216 mov r2, r0
217 lsr r2, r2, #4
218 cmp r2, #0
219 ASM_ASSERT(eq)
220
221 /* val should be between [0, 65535] */
222 mov r2, r1
223 lsr r2, r2, #16
224 cmp r2, #0
225 ASM_ASSERT(eq)
226#endif
227
228 /*
229 * Given `idx` calculate address of stcopr/bx lr instruction pair
230 * in the table below.
231 */
232 adr r2, 1f
233 lsl r0, r0, #3 /* each stcopr/bx lr sequence is 8 bytes */
234 add r2, r2, r0
235 bx r2
236
2371:
johpow01fa59c6f2020-10-02 13:41:11 -0500238 stcopr r1, AMEVTYPER10 /* index 0 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000239 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500240 stcopr r1, AMEVTYPER11 /* index 1 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000241 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500242 stcopr r1, AMEVTYPER12 /* index 2 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000243 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500244 stcopr r1, AMEVTYPER13 /* index 3 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000245 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500246 stcopr r1, AMEVTYPER14 /* index 4 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000247 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500248 stcopr r1, AMEVTYPER15 /* index 5 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000249 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500250 stcopr r1, AMEVTYPER16 /* index 6 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000251 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500252 stcopr r1, AMEVTYPER17 /* index 7 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000253 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500254 stcopr r1, AMEVTYPER18 /* index 8 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000255 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500256 stcopr r1, AMEVTYPER19 /* index 9 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000257 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500258 stcopr r1, AMEVTYPER1A /* index 10 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000259 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500260 stcopr r1, AMEVTYPER1B /* index 11 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000261 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500262 stcopr r1, AMEVTYPER1C /* index 12 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000263 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500264 stcopr r1, AMEVTYPER1D /* index 13 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000265 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500266 stcopr r1, AMEVTYPER1E /* index 14 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000267 bx lr
johpow01fa59c6f2020-10-02 13:41:11 -0500268 stcopr r1, AMEVTYPER1F /* index 15 */
Joel Hutton2691bc62017-12-12 15:47:55 +0000269 bx lr
270endfunc amu_group1_set_evtype_internal
Chris Kay925fda42021-05-25 10:42:56 +0100271#endif