Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 2 | * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <console.h> |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 9 | #include <debug.h> |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 10 | #include <mmio.h> |
| 11 | #include <plat_arm.h> |
| 12 | #include <platform.h> |
| 13 | #include <platform_def.h> |
| 14 | #include <platform_sp_min.h> |
| 15 | |
| 16 | #define BL32_END (uintptr_t)(&__BL32_END__) |
| 17 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 18 | static entry_point_info_t bl33_image_ep_info; |
| 19 | |
| 20 | /* Weak definitions may be overridden in specific ARM standard platform */ |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 21 | #pragma weak sp_min_platform_setup |
| 22 | #pragma weak sp_min_plat_arch_setup |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 23 | #pragma weak plat_arm_sp_min_early_platform_setup |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 24 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 25 | |
| 26 | /******************************************************************************* |
| 27 | * Return a pointer to the 'entry_point_info' structure of the next image for the |
| 28 | * security state specified. BL33 corresponds to the non-secure image type |
| 29 | * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| 30 | * if the image does not exist. |
| 31 | ******************************************************************************/ |
| 32 | entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) |
| 33 | { |
| 34 | entry_point_info_t *next_image_info; |
| 35 | |
| 36 | next_image_info = &bl33_image_ep_info; |
| 37 | |
| 38 | /* |
| 39 | * None of the images on the ARM development platforms can have 0x0 |
| 40 | * as the entrypoint |
| 41 | */ |
| 42 | if (next_image_info->pc) |
| 43 | return next_image_info; |
| 44 | else |
| 45 | return NULL; |
| 46 | } |
| 47 | |
| 48 | /******************************************************************************* |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 49 | * Utility function to perform early platform setup. |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 50 | ******************************************************************************/ |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 51 | void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, |
| 52 | uintptr_t hw_config, void *plat_params_from_bl2) |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 53 | { |
| 54 | /* Initialize the console to provide early debug support */ |
| 55 | console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, |
| 56 | ARM_CONSOLE_BAUDRATE); |
| 57 | |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 58 | #if RESET_TO_SP_MIN |
| 59 | /* There are no parameters from BL2 if SP_MIN is a reset vector */ |
| 60 | assert(from_bl2 == NULL); |
| 61 | assert(plat_params_from_bl2 == NULL); |
| 62 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 63 | /* Populate entry point information for BL33 */ |
| 64 | SET_PARAM_HEAD(&bl33_image_ep_info, |
| 65 | PARAM_EP, |
| 66 | VERSION_1, |
| 67 | 0); |
| 68 | /* |
| 69 | * Tell SP_MIN where the non-trusted software image |
| 70 | * is located and the entry state information |
| 71 | */ |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 72 | bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 73 | bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); |
| 74 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 75 | |
| 76 | #else /* RESET_TO_SP_MIN */ |
| 77 | |
| 78 | /* |
| 79 | * Check params passed from BL2 should not be NULL, |
| 80 | */ |
| 81 | bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; |
| 82 | assert(params_from_bl2 != NULL); |
| 83 | assert(params_from_bl2->h.type == PARAM_BL_PARAMS); |
| 84 | assert(params_from_bl2->h.version >= VERSION_2); |
| 85 | |
| 86 | bl_params_node_t *bl_params = params_from_bl2->head; |
| 87 | |
| 88 | /* |
| 89 | * Copy BL33 entry point information. |
| 90 | * They are stored in Secure RAM, in BL2's address space. |
| 91 | */ |
| 92 | while (bl_params) { |
| 93 | if (bl_params->image_id == BL33_IMAGE_ID) { |
| 94 | bl33_image_ep_info = *bl_params->ep_info; |
| 95 | break; |
| 96 | } |
| 97 | |
| 98 | bl_params = bl_params->next_params_info; |
| 99 | } |
| 100 | |
| 101 | if (bl33_image_ep_info.pc == 0) |
| 102 | panic(); |
| 103 | |
| 104 | #endif /* RESET_TO_SP_MIN */ |
| 105 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 106 | } |
| 107 | |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 108 | /******************************************************************************* |
| 109 | * Default implementation for sp_min_platform_setup2() for ARM platforms |
| 110 | ******************************************************************************/ |
| 111 | void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 112 | u_register_t arg2, u_register_t arg3) |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 113 | { |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 114 | arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * Initialize Interconnect for this cluster during cold boot. |
| 118 | * No need for locks as no other CPU is active. |
| 119 | */ |
| 120 | plat_arm_interconnect_init(); |
| 121 | |
| 122 | /* |
| 123 | * Enable Interconnect coherency for the primary CPU's cluster. |
| 124 | * Earlier bootloader stages might already do this (e.g. Trusted |
| 125 | * Firmware's BL1 does it) but we can't assume so. There is no harm in |
| 126 | * executing this code twice anyway. |
| 127 | * Platform specific PSCI code will enable coherency for other |
| 128 | * clusters. |
| 129 | */ |
| 130 | plat_arm_interconnect_enter_coherency(); |
| 131 | } |
| 132 | |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 133 | void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 134 | u_register_t arg2, u_register_t arg3) |
| 135 | { |
| 136 | plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); |
| 137 | } |
| 138 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 139 | /******************************************************************************* |
Dimitris Papastamos | 52323b0 | 2017-06-07 13:45:41 +0100 | [diff] [blame] | 140 | * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. |
| 141 | * Common to ARM standard platforms. |
| 142 | ******************************************************************************/ |
| 143 | void arm_sp_min_plat_runtime_setup(void) |
| 144 | { |
| 145 | /* Initialize the runtime console */ |
| 146 | console_init(PLAT_ARM_SP_MIN_RUN_UART_BASE, |
| 147 | PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE); |
| 148 | } |
| 149 | |
| 150 | /******************************************************************************* |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 151 | * Perform platform specific setup for SP_MIN |
| 152 | ******************************************************************************/ |
| 153 | void sp_min_platform_setup(void) |
| 154 | { |
| 155 | /* Initialize the GIC driver, cpu and distributor interfaces */ |
| 156 | plat_arm_gic_driver_init(); |
| 157 | plat_arm_gic_init(); |
| 158 | |
| 159 | /* |
| 160 | * Do initial security configuration to allow DRAM/device access |
| 161 | * (if earlier BL has not already done so). |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 162 | */ |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 163 | #if RESET_TO_SP_MIN |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 164 | plat_arm_security_setup(); |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 165 | #endif |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 166 | |
| 167 | /* Enable and initialize the System level generic timer */ |
| 168 | mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, |
| 169 | CNTCR_FCREQ(0) | CNTCR_EN); |
| 170 | |
| 171 | /* Allow access to the System counter timer module */ |
| 172 | arm_configure_sys_timer(); |
| 173 | |
| 174 | /* Initialize power controller before setting up topology */ |
| 175 | plat_arm_pwrc_setup(); |
| 176 | } |
| 177 | |
Dimitris Papastamos | 52323b0 | 2017-06-07 13:45:41 +0100 | [diff] [blame] | 178 | void sp_min_plat_runtime_setup(void) |
| 179 | { |
| 180 | arm_sp_min_plat_runtime_setup(); |
| 181 | } |
| 182 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 183 | /******************************************************************************* |
| 184 | * Perform the very early platform specific architectural setup here. At the |
| 185 | * moment this only initializes the MMU |
| 186 | ******************************************************************************/ |
| 187 | void sp_min_plat_arch_setup(void) |
| 188 | { |
| 189 | |
| 190 | arm_setup_page_tables(BL32_BASE, |
| 191 | (BL32_END - BL32_BASE), |
| 192 | BL_CODE_BASE, |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 193 | BL_CODE_END, |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 194 | BL_RO_DATA_BASE, |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 195 | BL_RO_DATA_END |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 196 | #if USE_COHERENT_MEM |
Masahiro Yamada | 0fac5af | 2016-12-28 16:11:41 +0900 | [diff] [blame] | 197 | , BL_COHERENT_RAM_BASE, |
| 198 | BL_COHERENT_RAM_END |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 199 | #endif |
| 200 | ); |
| 201 | |
| 202 | enable_mmu_secure(0); |
| 203 | } |