Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 1 | /* |
Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 2 | * Copyright (c) 2020-2021, Arm Limited. All rights reserved. |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <cpu_macros.S> |
| 10 | #include <neoverse_n2.h> |
| 11 | |
| 12 | /* Hardware handled coherency */ |
| 13 | #if HW_ASSISTED_COHERENCY == 0 |
| 14 | #error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 15 | #endif |
| 16 | |
| 17 | /* 64-bit only core */ |
| 18 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 19 | #error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 20 | #endif |
| 21 | |
nayanpatel-arm | 277581e | 2021-08-06 17:46:10 -0700 | [diff] [blame] | 22 | /* -------------------------------------------------- |
| 23 | * Errata Workaround for Neoverse N2 Erratum 2002655. |
| 24 | * This applies to revision r0p0 of Neoverse N2. it is still open. |
| 25 | * Inputs: |
| 26 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 27 | * Shall clobber: x0-x17 |
| 28 | * -------------------------------------------------- |
| 29 | */ |
| 30 | func errata_n2_2002655_wa |
| 31 | /* Check revision. */ |
| 32 | mov x17, x30 |
| 33 | bl check_errata_2002655 |
| 34 | cbz x0, 1f |
| 35 | |
| 36 | /* Apply instruction patching sequence */ |
| 37 | ldr x0,=0x6 |
| 38 | msr S3_6_c15_c8_0,x0 |
| 39 | ldr x0,=0xF3A08002 |
| 40 | msr S3_6_c15_c8_2,x0 |
| 41 | ldr x0,=0xFFF0F7FE |
| 42 | msr S3_6_c15_c8_3,x0 |
| 43 | ldr x0,=0x40000001003ff |
| 44 | msr S3_6_c15_c8_1,x0 |
| 45 | ldr x0,=0x7 |
| 46 | msr S3_6_c15_c8_0,x0 |
| 47 | ldr x0,=0xBF200000 |
| 48 | msr S3_6_c15_c8_2,x0 |
| 49 | ldr x0,=0xFFEF0000 |
| 50 | msr S3_6_c15_c8_3,x0 |
| 51 | ldr x0,=0x40000001003f3 |
| 52 | msr S3_6_c15_c8_1,x0 |
| 53 | isb |
| 54 | 1: |
| 55 | ret x17 |
| 56 | endfunc errata_n2_2002655_wa |
| 57 | |
| 58 | func check_errata_2002655 |
| 59 | /* Applies to r0p0 */ |
| 60 | mov x1, #0x00 |
| 61 | b cpu_rev_var_ls |
| 62 | endfunc check_errata_2002655 |
| 63 | |
Bipin Ravi | eb35e85 | 2021-03-30 16:08:32 -0500 | [diff] [blame] | 64 | /* --------------------------------------------------------------- |
| 65 | * Errata Workaround for Neoverse N2 Erratum 2067956. |
| 66 | * This applies to revision r0p0 of Neoverse N2 and is still open. |
| 67 | * Inputs: |
| 68 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 69 | * Shall clobber: x0-x17 |
| 70 | * --------------------------------------------------------------- |
| 71 | */ |
| 72 | func errata_n2_2067956_wa |
| 73 | /* Compare x0 against revision r0p0 */ |
| 74 | mov x17, x30 |
| 75 | bl check_errata_2067956 |
| 76 | cbz x0, 1f |
| 77 | mrs x1, NEOVERSE_N2_CPUACTLR_EL1 |
| 78 | orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 |
| 79 | msr NEOVERSE_N2_CPUACTLR_EL1, x1 |
| 80 | 1: |
| 81 | ret x17 |
| 82 | endfunc errata_n2_2067956_wa |
| 83 | |
| 84 | func check_errata_2067956 |
| 85 | /* Applies to r0p0 */ |
| 86 | mov x1, #0x00 |
| 87 | b cpu_rev_var_ls |
| 88 | endfunc check_errata_2067956 |
| 89 | |
Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 90 | /* --------------------------------------------------------------- |
| 91 | * Errata Workaround for Neoverse N2 Erratum 2025414. |
| 92 | * This applies to revision r0p0 of Neoverse N2 and is still open. |
| 93 | * Inputs: |
| 94 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 95 | * Shall clobber: x0-x17 |
| 96 | * --------------------------------------------------------------- |
| 97 | */ |
| 98 | func errata_n2_2025414_wa |
| 99 | /* Compare x0 against revision r0p0 */ |
| 100 | mov x17, x30 |
| 101 | bl check_errata_2025414 |
| 102 | cbz x0, 1f |
| 103 | mrs x1, NEOVERSE_N2_CPUECTLR_EL1 |
| 104 | orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT |
| 105 | msr NEOVERSE_N2_CPUECTLR_EL1, x1 |
| 106 | |
| 107 | 1: |
| 108 | ret x17 |
| 109 | endfunc errata_n2_2025414_wa |
| 110 | |
| 111 | func check_errata_2025414 |
| 112 | /* Applies to r0p0 */ |
| 113 | mov x1, #0x00 |
| 114 | b cpu_rev_var_ls |
| 115 | endfunc check_errata_2025414 |
| 116 | |
Bipin Ravi | 7e03069 | 2021-08-30 13:02:51 -0500 | [diff] [blame] | 117 | /* --------------------------------------------------------------- |
| 118 | * Errata Workaround for Neoverse N2 Erratum 2189731. |
| 119 | * This applies to revision r0p0 of Neoverse N2 and is still open. |
| 120 | * Inputs: |
| 121 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 122 | * Shall clobber: x0-x17 |
| 123 | * --------------------------------------------------------------- |
| 124 | */ |
| 125 | func errata_n2_2189731_wa |
| 126 | /* Compare x0 against revision r0p0 */ |
| 127 | mov x17, x30 |
| 128 | bl check_errata_2189731 |
| 129 | cbz x0, 1f |
| 130 | mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 |
| 131 | orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 |
| 132 | msr NEOVERSE_N2_CPUACTLR5_EL1, x1 |
| 133 | |
| 134 | 1: |
| 135 | ret x17 |
| 136 | endfunc errata_n2_2189731_wa |
| 137 | |
| 138 | func check_errata_2189731 |
| 139 | /* Applies to r0p0 */ |
| 140 | mov x1, #0x00 |
| 141 | b cpu_rev_var_ls |
| 142 | endfunc check_errata_2189731 |
| 143 | |
Bipin Ravi | 0ba631c | 2021-09-01 01:36:43 -0500 | [diff] [blame] | 144 | /* -------------------------------------------------- |
| 145 | * Errata Workaround for Neoverse N2 Erratum 2138956. |
| 146 | * This applies to revision r0p0 of Neoverse N2. it is still open. |
| 147 | * Inputs: |
| 148 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 149 | * Shall clobber: x0-x17 |
| 150 | * -------------------------------------------------- |
| 151 | */ |
| 152 | func errata_n2_2138956_wa |
| 153 | /* Check revision. */ |
| 154 | mov x17, x30 |
| 155 | bl check_errata_2138956 |
| 156 | cbz x0, 1f |
| 157 | |
| 158 | /* Apply instruction patching sequence */ |
| 159 | ldr x0,=0x3 |
| 160 | msr S3_6_c15_c8_0,x0 |
| 161 | ldr x0,=0xF3A08002 |
| 162 | msr S3_6_c15_c8_2,x0 |
| 163 | ldr x0,=0xFFF0F7FE |
| 164 | msr S3_6_c15_c8_3,x0 |
| 165 | ldr x0,=0x10002001003FF |
| 166 | msr S3_6_c15_c8_1,x0 |
| 167 | ldr x0,=0x4 |
| 168 | msr S3_6_c15_c8_0,x0 |
| 169 | ldr x0,=0xBF200000 |
| 170 | msr S3_6_c15_c8_2,x0 |
| 171 | ldr x0,=0xFFEF0000 |
| 172 | msr S3_6_c15_c8_3,x0 |
| 173 | ldr x0,=0x10002001003F3 |
| 174 | msr S3_6_c15_c8_1,x0 |
| 175 | isb |
| 176 | 1: |
| 177 | ret x17 |
| 178 | endfunc errata_n2_2138956_wa |
| 179 | |
| 180 | func check_errata_2138956 |
| 181 | /* Applies to r0p0 */ |
| 182 | mov x1, #0x00 |
| 183 | b cpu_rev_var_ls |
| 184 | endfunc check_errata_2138956 |
| 185 | |
Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 186 | /* ------------------------------------------- |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 187 | * The CPU Ops reset function for Neoverse N2. |
Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 188 | * ------------------------------------------- |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 189 | */ |
| 190 | func neoverse_n2_reset_func |
nayanpatel-arm | 277581e | 2021-08-06 17:46:10 -0700 | [diff] [blame] | 191 | mov x19, x30 |
| 192 | |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 193 | /* Check if the PE implements SSBS */ |
| 194 | mrs x0, id_aa64pfr1_el1 |
| 195 | tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) |
| 196 | b.eq 1f |
| 197 | |
| 198 | /* Disable speculative loads */ |
| 199 | msr SSBS, xzr |
| 200 | 1: |
| 201 | /* Force all cacheable atomic instructions to be near */ |
| 202 | mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 |
| 203 | orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 |
| 204 | msr NEOVERSE_N2_CPUACTLR2_EL1, x0 |
| 205 | |
Bipin Ravi | eb35e85 | 2021-03-30 16:08:32 -0500 | [diff] [blame] | 206 | #if ERRATA_N2_2067956 |
| 207 | mov x0, x18 |
| 208 | bl errata_n2_2067956_wa |
| 209 | #endif |
| 210 | |
Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 211 | #if ERRATA_N2_2025414 |
| 212 | mov x0, x18 |
| 213 | bl errata_n2_2025414_wa |
| 214 | #endif |
| 215 | |
Bipin Ravi | 7e03069 | 2021-08-30 13:02:51 -0500 | [diff] [blame] | 216 | #if ERRATA_N2_2189731 |
| 217 | mov x0, x18 |
| 218 | bl errata_n2_2189731_wa |
| 219 | #endif |
| 220 | |
Bipin Ravi | 0ba631c | 2021-09-01 01:36:43 -0500 | [diff] [blame] | 221 | |
| 222 | #if ERRATA_N2_2138956 |
| 223 | mov x0, x18 |
| 224 | bl errata_n2_2138956_wa |
| 225 | #endif |
| 226 | |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 227 | #if ENABLE_AMU |
| 228 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 229 | mrs x0, cptr_el3 |
| 230 | orr x0, x0, #TAM_BIT |
| 231 | msr cptr_el3, x0 |
| 232 | |
| 233 | /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
| 234 | mrs x0, cptr_el2 |
| 235 | orr x0, x0, #TAM_BIT |
| 236 | msr cptr_el2, x0 |
| 237 | |
| 238 | /* No need to enable the counters as this would be done at el3 exit */ |
| 239 | #endif |
| 240 | |
| 241 | #if NEOVERSE_Nx_EXTERNAL_LLC |
| 242 | /* Some systems may have External LLC, core needs to be made aware */ |
Bipin Ravi | eb35e85 | 2021-03-30 16:08:32 -0500 | [diff] [blame] | 243 | mrs x0, NEOVERSE_N2_CPUECTLR_EL1 |
| 244 | orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT |
| 245 | msr NEOVERSE_N2_CPUECTLR_EL1, x0 |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 246 | #endif |
| 247 | |
nayanpatel-arm | 277581e | 2021-08-06 17:46:10 -0700 | [diff] [blame] | 248 | bl cpu_get_rev_var |
| 249 | mov x18, x0 |
| 250 | |
| 251 | #if ERRATA_N2_2002655 |
| 252 | mov x0, x18 |
| 253 | bl errata_n2_2002655_wa |
| 254 | #endif |
| 255 | |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 256 | isb |
Bipin Ravi | eb35e85 | 2021-03-30 16:08:32 -0500 | [diff] [blame] | 257 | ret x19 |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 258 | endfunc neoverse_n2_reset_func |
| 259 | |
| 260 | func neoverse_n2_core_pwr_dwn |
Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 261 | /* --------------------------------------------------- |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 262 | * Enable CPU power down bit in power control register |
| 263 | * No need to do cache maintenance here. |
Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 264 | * --------------------------------------------------- |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 265 | */ |
| 266 | mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 |
| 267 | orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT |
| 268 | msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 |
| 269 | isb |
| 270 | ret |
| 271 | endfunc neoverse_n2_core_pwr_dwn |
| 272 | |
| 273 | #if REPORT_ERRATA |
| 274 | /* |
| 275 | * Errata printing function for Neoverse N2 cores. Must follow AAPCS. |
| 276 | */ |
| 277 | func neoverse_n2_errata_report |
nayanpatel-arm | 277581e | 2021-08-06 17:46:10 -0700 | [diff] [blame] | 278 | stp x8, x30, [sp, #-16]! |
| 279 | |
| 280 | bl cpu_get_rev_var |
| 281 | mov x8, x0 |
| 282 | |
| 283 | /* |
| 284 | * Report all errata. The revision-variant information is passed to |
| 285 | * checking functions of each errata. |
| 286 | */ |
| 287 | report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 |
Bipin Ravi | eb35e85 | 2021-03-30 16:08:32 -0500 | [diff] [blame] | 288 | report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 |
Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 289 | report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 |
Bipin Ravi | 7e03069 | 2021-08-30 13:02:51 -0500 | [diff] [blame] | 290 | report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 |
Bipin Ravi | 0ba631c | 2021-09-01 01:36:43 -0500 | [diff] [blame] | 291 | report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 |
nayanpatel-arm | 277581e | 2021-08-06 17:46:10 -0700 | [diff] [blame] | 292 | |
| 293 | ldp x8, x30, [sp], #16 |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 294 | ret |
| 295 | endfunc neoverse_n2_errata_report |
| 296 | #endif |
| 297 | |
| 298 | /* --------------------------------------------- |
| 299 | * This function provides Neoverse N2 specific |
| 300 | * register information for crash reporting. |
| 301 | * It needs to return with x6 pointing to |
| 302 | * a list of register names in ASCII and |
| 303 | * x8 - x15 having values of registers to be |
| 304 | * reported. |
| 305 | * --------------------------------------------- |
| 306 | */ |
| 307 | .section .rodata.neoverse_n2_regs, "aS" |
| 308 | neoverse_n2_regs: /* The ASCII list of register names to be reported */ |
| 309 | .asciz "cpupwrctlr_el1", "" |
| 310 | |
| 311 | func neoverse_n2_cpu_reg_dump |
| 312 | adr x6, neoverse_n2_regs |
| 313 | mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 |
| 314 | ret |
| 315 | endfunc neoverse_n2_cpu_reg_dump |
| 316 | |
| 317 | declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ |
| 318 | neoverse_n2_reset_func, \ |
| 319 | neoverse_n2_core_pwr_dwn |