Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <asm_macros.S> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <psci.h> |
Achin Gupta | e1aa516 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 34 | #include <xlat_tables.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | |
| 36 | .globl psci_aff_on_finish_entry |
| 37 | .globl psci_aff_suspend_finish_entry |
| 38 | .globl __psci_cpu_off |
| 39 | .globl __psci_cpu_suspend |
Achin Gupta | 42c5280 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 40 | .globl psci_power_down_wfi |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 41 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 42 | /* ----------------------------------------------------- |
| 43 | * This cpu has been physically powered up. Depending |
| 44 | * upon whether it was resumed from suspend or simply |
| 45 | * turned on, call the common power on finisher with |
| 46 | * the handlers (chosen depending upon original state). |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | * ----------------------------------------------------- |
| 48 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 49 | func psci_aff_on_finish_entry |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 50 | adr x23, psci_afflvl_on_finishers |
| 51 | b psci_aff_common_finish_entry |
| 52 | |
| 53 | psci_aff_suspend_finish_entry: |
| 54 | adr x23, psci_afflvl_suspend_finishers |
| 55 | |
| 56 | psci_aff_common_finish_entry: |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 57 | /* --------------------------------------------- |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 58 | * Initialise the pcpu cache pointer for the CPU |
| 59 | * --------------------------------------------- |
| 60 | */ |
| 61 | bl init_cpu_data_ptr |
| 62 | |
| 63 | /* --------------------------------------------- |
Andrew Thoelke | 4d2d553 | 2014-06-02 12:38:12 +0100 | [diff] [blame] | 64 | * Set the exception vectors |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 65 | * --------------------------------------------- |
| 66 | */ |
Andrew Thoelke | 4d2d553 | 2014-06-02 12:38:12 +0100 | [diff] [blame] | 67 | adr x0, runtime_exceptions |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 68 | msr vbar_el3, x0 |
| 69 | isb |
| 70 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 71 | /* --------------------------------------------- |
| 72 | * Use SP_EL0 for the C runtime stack. |
| 73 | * --------------------------------------------- |
| 74 | */ |
| 75 | msr spsel, #0 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 76 | |
Achin Gupta | e1aa516 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 77 | /* -------------------------------------------- |
| 78 | * Give ourselves a stack whose memory will be |
| 79 | * marked as Normal-IS-WBWA when the MMU is |
| 80 | * enabled. |
| 81 | * -------------------------------------------- |
| 82 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 83 | mrs x0, mpidr_el1 |
Achin Gupta | e1aa516 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 84 | bl platform_set_stack |
| 85 | |
| 86 | /* -------------------------------------------- |
| 87 | * Enable the MMU with the DCache disabled. It |
| 88 | * is safe to use stacks allocated in normal |
| 89 | * memory as a result. All memory accesses are |
| 90 | * marked nGnRnE when the MMU is disabled. So |
| 91 | * all the stack writes will make it to memory. |
| 92 | * All memory accesses are marked Non-cacheable |
| 93 | * when the MMU is enabled but D$ is disabled. |
| 94 | * So used stack memory is guaranteed to be |
| 95 | * visible immediately after the MMU is enabled |
| 96 | * Enabling the DCache at the same time as the |
| 97 | * MMU can lead to speculatively fetched and |
| 98 | * possibly stale stack memory being read from |
| 99 | * other caches. This can lead to coherency |
| 100 | * issues. |
| 101 | * -------------------------------------------- |
| 102 | */ |
| 103 | mov x0, #DISABLE_DCACHE |
| 104 | bl bl31_plat_enable_mmu |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 105 | |
| 106 | /* --------------------------------------------- |
| 107 | * Call the finishers starting from affinity |
| 108 | * level 0. |
| 109 | * --------------------------------------------- |
| 110 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 111 | mrs x0, mpidr_el1 |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 112 | bl get_power_on_target_afflvl |
| 113 | cmp x0, xzr |
| 114 | b.lt _panic |
Andrew Thoelke | 2bc0785 | 2014-06-09 12:44:21 +0100 | [diff] [blame] | 115 | mov x2, x23 |
| 116 | mov x1, x0 |
| 117 | mov x0, #MPIDR_AFFLVL0 |
| 118 | bl psci_afflvl_power_on_finish |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 119 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 120 | b el3_exit |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 121 | _panic: |
| 122 | b _panic |
| 123 | |
Achin Gupta | 42c5280 | 2014-05-09 19:32:25 +0100 | [diff] [blame] | 124 | /* -------------------------------------------- |
| 125 | * This function is called to indicate to the |
| 126 | * power controller that it is safe to power |
| 127 | * down this cpu. It should not exit the wfi |
| 128 | * and will be released from reset upon power |
| 129 | * up. 'wfi_spill' is used to catch erroneous |
| 130 | * exits from wfi. |
| 131 | * -------------------------------------------- |
| 132 | */ |
| 133 | func psci_power_down_wfi |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 134 | dsb sy // ensure write buffer empty |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 135 | wfi |
| 136 | wfi_spill: |
| 137 | b wfi_spill |
| 138 | |