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Peng Fan7af02142017-07-05 16:34:37 +08001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef TZC380_H
8#define TZC380_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <drivers/arm/tzc_common.h>
11#include <lib/utils_def.h>
Peng Fan7af02142017-07-05 16:34:37 +080012
13#define TZC380_CONFIGURATION_OFF U(0x000)
14#define ACTION_OFF U(0x004)
15#define LOCKDOWN_RANGE_OFF U(0x008)
16#define LOCKDOWN_SELECT_OFF U(0x00C)
17#define INT_STATUS U(0x010)
18#define INT_CLEAR U(0x014)
19
20#define FAIL_ADDRESS_LOW_OFF U(0x020)
21#define FAIL_ADDRESS_HIGH_OFF U(0x024)
22#define FAIL_CONTROL_OFF U(0x028)
23#define FAIL_ID U(0x02c)
24
25#define SPECULATION_CTRL_OFF U(0x030)
26#define SECURITY_INV_EN_OFF U(0x034)
27
28#define REGION_SETUP_LOW_OFF(n) U(0x100 + (n) * 0x10)
29#define REGION_SETUP_HIGH_OFF(n) U(0x104 + (n) * 0x10)
30#define REGION_ATTRIBUTES_OFF(n) U(0x108 + (n) * 0x10)
31
32#define BUILD_CONFIG_AW_SHIFT 8
33#define BUILD_CONFIG_AW_MASK U(0x3f)
34#define BUILD_CONFIG_NR_SHIFT 0
35#define BUILD_CONFIG_NR_MASK U(0xf)
36
37#define ACTION_RV_SHIFT 0
38#define ACTION_RV_MASK U(0x3)
39#define ACTION_RV_LOWOK U(0x0)
40#define ACTION_RV_LOWERR U(0x1)
41#define ACTION_RV_HIGHOK U(0x2)
42#define ACTION_RV_HIGHERR U(0x3)
43
44/* Speculation is enabled by default. */
45#define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
46#define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
47
48#define INT_STATUS_OVERRUN_SHIFT 1
49#define INT_STATUS_OVERRUN_MASK U(0x1)
50#define INT_STATUS_STATUS_SHIFT 0
51#define INT_STATUS_STATUS_MASK U(0x1)
52
53#define INT_CLEAR_CLEAR_SHIFT 0
54#define INT_CLEAR_CLEAR_MASK U(0x1)
55
56#define TZC380_COMPONENT_ID U(0xb105f00d)
57#define TZC380_PERIPH_ID_LOW U(0x001bb380)
58#define TZC380_PERIPH_ID_HIGH U(0x00000004)
59
60#define TZC_SP_NS_W BIT_32(0)
61#define TZC_SP_NS_R BIT_32(1)
62#define TZC_SP_S_W BIT_32(2)
63#define TZC_SP_S_R BIT_32(3)
64
65#define TZC_ATTR_SP_SHIFT 28
66#define TZC_ATTR_SP_ALL ((TZC_SP_S_W | TZC_SP_S_R | TZC_SP_NS_W | \
67 TZC_SP_NS_R) << TZC_ATTR_SP_SHIFT)
68#define TZC_ATTR_SP_S_RW ((TZC_SP_S_W | TZC_SP_S_R) << \
69 TZC_ATTR_SP_SHIFT)
70#define TZC_ATTR_SP_NS_RW ((TZC_SP_NS_W | TZC_SP_NS_R) << \
71 TZC_ATTR_SP_SHIFT)
72
73#define TZC_REGION_SIZE_32K U(0xe)
74#define TZC_REGION_SIZE_64K U(0xf)
75#define TZC_REGION_SIZE_128K U(0x10)
76#define TZC_REGION_SIZE_256K U(0x11)
77#define TZC_REGION_SIZE_512K U(0x12)
78#define TZC_REGION_SIZE_1M U(0x13)
79#define TZC_REGION_SIZE_2M U(0x14)
80#define TZC_REGION_SIZE_4M U(0x15)
81#define TZC_REGION_SIZE_8M U(0x16)
82#define TZC_REGION_SIZE_16M U(0x17)
83#define TZC_REGION_SIZE_32M U(0x18)
84#define TZC_REGION_SIZE_64M U(0x19)
85#define TZC_REGION_SIZE_128M U(0x1a)
86#define TZC_REGION_SIZE_256M U(0x1b)
87#define TZC_REGION_SIZE_512M U(0x1c)
88#define TZC_REGION_SIZE_1G U(0x1d)
89#define TZC_REGION_SIZE_2G U(0x1e)
90#define TZC_REGION_SIZE_4G U(0x1f)
91#define TZC_REGION_SIZE_8G U(0x20)
92#define TZC_REGION_SIZE_16G U(0x21)
93#define TZC_REGION_SIZE_32G U(0x22)
94#define TZC_REGION_SIZE_64G U(0x23)
95#define TZC_REGION_SIZE_128G U(0x24)
96#define TZC_REGION_SIZE_256G U(0x25)
97#define TZC_REGION_SIZE_512G U(0x26)
98#define TZC_REGION_SIZE_1T U(0x27)
99#define TZC_REGION_SIZE_2T U(0x28)
100#define TZC_REGION_SIZE_4T U(0x29)
101#define TZC_REGION_SIZE_8T U(0x2a)
102#define TZC_REGION_SIZE_16T U(0x2b)
103#define TZC_REGION_SIZE_32T U(0x2c)
104#define TZC_REGION_SIZE_64T U(0x2d)
105#define TZC_REGION_SIZE_128T U(0x2e)
106#define TZC_REGION_SIZE_256T U(0x2f)
107#define TZC_REGION_SIZE_512T U(0x30)
108#define TZC_REGION_SIZE_1P U(0x31)
109#define TZC_REGION_SIZE_2P U(0x32)
110#define TZC_REGION_SIZE_4P U(0x33)
111#define TZC_REGION_SIZE_8P U(0x34)
112#define TZC_REGION_SIZE_16P U(0x35)
113#define TZC_REGION_SIZE_32P U(0x36)
114#define TZC_REGION_SIZE_64P U(0x37)
115#define TZC_REGION_SIZE_128P U(0x38)
116#define TZC_REGION_SIZE_256P U(0x39)
117#define TZC_REGION_SIZE_512P U(0x3a)
118#define TZC_REGION_SIZE_1E U(0x3b)
119#define TZC_REGION_SIZE_2E U(0x3c)
120#define TZC_REGION_SIZE_4E U(0x3d)
121#define TZC_REGION_SIZE_8E U(0x3e)
122#define TZC_REGION_SIZE_16E U(0x3f)
123
124#define TZC_REGION_SIZE_SHIFT 0x1
125#define TZC_REGION_SIZE_MASK U(0x7e)
126#define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT)
127
128#define TZC_ATTR_REGION_EN_SHIFT 0x0
129#define TZC_ATTR_REGION_EN_MASK U(0x1)
130
131#define TZC_ATTR_REGION_EN
132#define TZC_ATTR_REGION_ENABLE U(0x1)
133#define TZC_ATTR_REGION_DISABLE U(0x0)
134
135#define REGION_MAX 16
136
137void tzc380_init(uintptr_t base);
138void tzc380_configure_region(uint8_t region,
139 uintptr_t region_base,
140 unsigned int attr);
Ambroise Vincent912c6302019-03-27 16:03:24 +0000141void tzc380_set_action(unsigned int action);
Peng Fan7af02142017-07-05 16:34:37 +0800142static inline void tzc_init(uintptr_t base)
143{
144 tzc380_init(base);
145}
146
147static inline void tzc_configure_region(uint8_t region,
148 uintptr_t region_base,
149 unsigned int attr)
150{
151 tzc380_configure_region(region, region_base, attr);
152}
153
Ambroise Vincent912c6302019-03-27 16:03:24 +0000154static inline void tzc_set_action(unsigned int action)
Peng Fan7af02142017-07-05 16:34:37 +0800155{
156 tzc380_set_action(action);
157}
158
159#endif /* TZC380_H */