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git01.mediatek.com / filogic / atf / 9e71911a6e624068980485371c36a34bb6dbe2d3 / . / plat / xilinx / versal / include / versal_def.h
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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]1/*
Michal Simek2a47faa2023-04-14 08:43:51 +0200[diff] [blame]2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700[diff] [blame]3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
Akshay Belsare589ccce2023-05-08 19:00:53 +0530[diff] [blame]4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef VERSAL_DEF_H
10#define VERSAL_DEF_H
11
Manish V Badarkhe55861512020-03-27 13:25:51 +0000[diff] [blame]12#include <plat/arm/common/smccc_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]13#include <plat/common/common_def.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]14
Akshay Belsare589ccce2023-05-08 19:00:53 +0530[diff] [blame]15#define PLATFORM_MASK GENMASK(27U, 24U)
16#define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
17
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700[diff] [blame]18/* number of interrupt handlers. increase as required */
19#define MAX_INTR_EL3 2
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]20/* List all consoles */
21#define VERSAL_CONSOLE_ID_pl011 1
22#define VERSAL_CONSOLE_ID_pl011_0 1
23#define VERSAL_CONSOLE_ID_pl011_1 2
24#define VERSAL_CONSOLE_ID_dcc 3
25
Michal Simekc56e5482023-09-27 13:58:06 +0200[diff] [blame]26#define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]27
28/* List all supported platforms */
29#define VERSAL_PLATFORM_ID_versal_virt 1
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +0530[diff] [blame]30#define VERSAL_PLATFORM_ID_spp_itr6 2
31#define VERSAL_PLATFORM_ID_emu_itr6 3
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +0530[diff] [blame]32#define VERSAL_PLATFORM_ID_silicon 4
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]33
34#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
35
36/* Firmware Image Package */
37#define VERSAL_PRIMARY_CPU 0
38
39/*******************************************************************************
40 * memory map related constants
41 ******************************************************************************/
42#define DEVICE0_BASE 0xFF000000
43#define DEVICE0_SIZE 0x00E00000
44#define DEVICE1_BASE 0xF9000000
45#define DEVICE1_SIZE 0x00800000
46
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]47/*******************************************************************************
48 * IRQ constants
49 ******************************************************************************/
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700[diff] [blame]50#define VERSAL_IRQ_SEC_PHY_TIMER U(29)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]51
52/*******************************************************************************
Tejas Patel54d13192019-02-27 18:44:55 +0530[diff] [blame]53 * CCI-400 related constants
54 ******************************************************************************/
55#define PLAT_ARM_CCI_BASE 0xFD000000
Michal Simek467e16e2023-04-14 08:39:49 +0200[diff] [blame]56#define PLAT_ARM_CCI_SIZE 0x00100000
Tejas Patel54d13192019-02-27 18:44:55 +0530[diff] [blame]57#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
58#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
59
60/*******************************************************************************
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]61 * UART related constants
62 ******************************************************************************/
63#define VERSAL_UART0_BASE 0xFF000000
64#define VERSAL_UART1_BASE 0xFF010000
65
Michal Simekc56e5482023-09-27 13:58:06 +0200[diff] [blame]66#if CONSOLE_IS(pl011) || CONSOLE_IS(dcc)
67# define UART_BASE VERSAL_UART0_BASE
68#elif CONSOLE_IS(pl011_1)
69# define UART_BASE VERSAL_UART1_BASE
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]70#else
71# error "invalid VERSAL_CONSOLE"
72#endif
73
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]74/*******************************************************************************
75 * Platform related constants
76 ******************************************************************************/
77#if VERSAL_PLATFORM_IS(versal_virt)
78# define PLATFORM_NAME "Versal Virt"
Michal Simekc56e5482023-09-27 13:58:06 +0200[diff] [blame]79# define UART_CLOCK 25000000
80# define UART_BAUDRATE 115200
Siva Durga Prasad Paladugu10161e52019-04-27 11:23:20 +0530[diff] [blame]81# define VERSAL_CPU_CLOCK 2720000
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +0530[diff] [blame]82#elif VERSAL_PLATFORM_IS(silicon)
83# define PLATFORM_NAME "Versal Silicon"
Michal Simekc56e5482023-09-27 13:58:06 +0200[diff] [blame]84# define UART_CLOCK 100000000
85# define UART_BAUDRATE 115200
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +0530[diff] [blame]86# define VERSAL_CPU_CLOCK 100000000
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +0530[diff] [blame]87#elif VERSAL_PLATFORM_IS(spp_itr6)
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +0530[diff] [blame]88# define PLATFORM_NAME "SPP ITR6"
Michal Simekc56e5482023-09-27 13:58:06 +0200[diff] [blame]89# define UART_CLOCK 25000000
90# define UART_BAUDRATE 115200
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +0530[diff] [blame]91# define VERSAL_CPU_CLOCK 2720000
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +0530[diff] [blame]92#elif VERSAL_PLATFORM_IS(emu_itr6)
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +0530[diff] [blame]93# define PLATFORM_NAME "EMU ITR6"
Michal Simekc56e5482023-09-27 13:58:06 +0200[diff] [blame]94# define UART_CLOCK 212000
95# define UART_BAUDRATE 9600
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +0530[diff] [blame]96# define VERSAL_CPU_CLOCK 212000
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]97#endif
98
99/* Access control register defines */
100#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
101#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
102
103/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
104#define CRF_BASE 0xFD1A0000
105#define CRF_SIZE 0x00600000
106
107/* CRF registers and bitfields */
108#define CRF_RST_APU (CRF_BASE + 0X00000300)
109
110#define CRF_RST_APU_ACPU_RESET (1 << 0)
111#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
112
113/* APU registers and bitfields */
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700[diff] [blame]114#define FPD_APU_BASE 0xFD5C0000U
115#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)
116#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U)
117#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U)
118#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]119
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700[diff] [blame]120#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U
121#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U
122#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]123
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700[diff] [blame]124/* PMC registers and bitfields */
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700[diff] [blame]125#define PMC_GLOBAL_BASE 0xF1110000U
126#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700[diff] [blame]127
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]128#endif /* VERSAL_DEF_H */